Through-Silicon Hole Interposers for 3-D IC Integration

Lau, John H.; Lee, Ching-Kuan; Zhan, Cheng; Wu, S. M.; Chao, Yu-Lin; Dai, Ming-Ji; Tain, Ra-Min; Chien, Heng-Chieh; Hung, Jui-Feng; Chien, Chun-Hsien; Cheng, Ren-Shing; Huang, Yu-Lieh; Cheng, Yu-Mei; Liao, Li-Ling; Lo, Wei‐Chung; Kao, Ming-Jer

doi:10.1109/tcpmt.2014.2339832

Cited by 39 publications

(5 citation statements)

References 18 publications

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“…In 3D ICs technology, the TSV interconnection in chip stacking is introduced to provide connectivity between different designed parts for proper signal propagation and delivery, especially in high bandwidth and high-density dynamic random access memory (DRAM) [ 38–42 ]. Sukharev [ 43 ] and Lau [ 44 ] reported finite element analysis simulations of TSV upon electromigration (EM) failure, which is when the TSV is unable to deliver the necessary voltage to any circuitry gate.…”

Section: Three-dimensional Integrated Circuits: the Technologymentioning

confidence: 99%

Intermetallic compounds in 3D integrated circuits technology: a brief review

Annuar

Mahmoodian

Hamdi

et al. 2017

Science and Technology of Advanced Materials

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The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

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Section: Three-dimensional Integrated Circuits: the Technologymentioning

confidence: 99%

Intermetallic compounds in 3D integrated circuits technology: a brief review

Annuar

Mahmoodian

Hamdi

et al. 2017

Science and Technology of Advanced Materials

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“…Because of the drive of AI, ML, and 5 G, the semiconductors such as the sliced field-programmable gate arrays density and I/Os increase and pad-pitch decreases. Even a 12 build-up layers (6-2-6), organic package substrate is not enough to support the sliced chips and a TSV-interposer is needed [121][122][123][124][125][126][127][128][129][130][131][132][133][134][135][136][137][138][139]. TSMC called this kind of structure CoWoS (chip-on-wafer-on substrate) [137,138].…”

Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…However, the back thinning technology significantly reduce its mechanical support capability and might damage the chip. TSV have great potential in the field of power IC heat dissipation due to their special structure and good thermal conductivity by filling metals with high thermal conductivity [21][22][23][24][25]. Many studies have focused on the application of TTSV in the thermal management of 3D IC, but not enough attention has been paid to its application in the thermal management of power chips [26][27][28][29][30].…”

Section: Introductionmentioning

confidence: 99%

Investigation of heat dissipation structure embedded in substrate of power chip based on grid-type thermal through silicon vias

Hu,

Lu,

Bai

et al. 2024

IEICE Electron. Express

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In the research on heat dissipation technology of power chips, the back thinning method is adopted. However, the back thinning technology is facing the risk of causing damage to the chips because the mechanical support capacity of the chip is significantly reduced. To improve the heat dissipation capacity of the back side of the power chips while not affecting the mechanical support, the back side grid type thermal TSV (GT-TTSV) heat dissipation structure is proposed. Based on the proposed heat transfer structure, the heat dissipation structure is optimized and verified, and compared with the heat dissipation structure of back thinning technology. Simulation comparative study shows that the proposed structure has better heat dissipation ability and thermal reliability.

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Through-Silicon Hole Interposers for 3-D IC Integration

Cited by 39 publications

References 18 publications

Intermetallic compounds in 3D integrated circuits technology: a brief review

Intermetallic compounds in 3D integrated circuits technology: a brief review

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Investigation of heat dissipation structure embedded in substrate of power chip based on grid-type thermal through silicon vias

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