Through-Silicon-Via resistive-open defect analysis

Metzler, C.; Todri, A.; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Virazel, Arnaud

doi:10.1109/ets.2012.6233037

Cited by 10 publications

(3 citation statements)

References 4 publications

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“…Moreover, path delays in a 3D-IC already experience variations due to the physical and electrical conditions [3]- [6] such as nonuniform switching, supply noise (such as IR-drop), TSVto-TSV coupling and coupling through the lossy substrate. These conditions tend to affect path delay and may result in incremental signal delay through the path or even cause artificial speed-up or slow-down due to different voltage potentials between driver and receiver gates.…”

Section: Introductionmentioning

confidence: 99%

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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International audienceThrough-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools

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Section: Introductionmentioning

confidence: 99%

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

Self Cite

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“…The main issues regarding the use of TSVs are the large area overhead of TSV pitches, the yield reduction caused by the large number of TSVs, and TSV cost. Moreover, the manufacturing process of TSVs has become a main challenge due to the variability of the manufacturing process [2] [3]. The cost of high yield TSV manufacturing process is only justifiable in presence of a practical solution to counteract TSV related effects (such as voids in TSVs, TSV pinch-off, oxide defects such as pinholes, thermo-mechanical stress, cracks in microbumps, chip warpage, and impurities [4]) which may render the entire chip useless [5].…”

Section: Introductionmentioning

confidence: 99%

CoBRA: Low cost compensation of TSV failures in 3D-NoC

Salamat

Ebrahimi

Bagherzadeh

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abstract-3D-NoC has emerged to provide fast and power efficient connection between the layers of 2D-NoCs using Through-Silicon-Vias (TSV). Thermal stress, warpage, impurities and misalignment during the manufacturing process make these expensive TSVs vulnerable to faults. Chips with faulty TSVs should be either discarded or utilized by providing a proper fault-tolerant method. In this paper, we target designing a reconfigurable fault-tolerant routing algorithm capable of tolerating fabrication-time or run-time TSV failures. The proposed algorithm ensures a fault-free communication between any two nodes in the presence of TSV failures. Experimental results show that the proposed fault-tolerant routing algorithm provides 100% reliability as long as there is one healthy TSV in the eastmost or westmost column. The reliability of the counterpart algorithm, the Elevator-first routing algorithm, drops to 75% and 45% in presence of one and two faulty TSVs, respectively.

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“…Τα πιθανά σφάλματα που περιορίζουν την περαιτέρω βελτίωση της τεχνολογίας περιλαμβάνουν τρύπες κενού και σπασίματα στα TSV, κακώς ευθυγραμισμένα ολοκληρωμένα κυκλώματα, αποτυχίες καθαρότητας υλικού, βραχυκύκλωμα προς το υπόστρωμα, αποκόλληση του bump από το ολοκληρωμένο, κ.α. [64][65][66].…”

Section: μοντελοποίηση βλαβών σε διασυνδέσεις διαμέσου πυριτίου (Tsv) 41 εισαγωγήunclassified

Μοντελοποίηση Θορύβου Και Διασυνδέσεων Διαμέσου Πυριτίου (TSV) Και Μελέτη Μεθόδων Διάγνωσης Βλαβών Σε Τρισδιάστατα Ολοκληρωμένα Κυκλώματα Στις Υψηλές Συχνότητες (RF)

Γεράκης¹

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Σκοπός της διατριβής ήταν η μελέτη και μοντελοποίηση της ηλεκτρομαγνητικής σύζευξης μεταλλικών γραμμών και ολοκληρωμένων πηνίων διαμέσου του υποστρώματος πυριτίου και της διαστρωμάτωσης των διαφόρων επιπέδων οξειδίων επάνω στο πυρίτιο στα ολοκληρωμένα κυκλώματα. Επίσης, αναπτύχθηκαν μέθοδοι μοντελοποίησης στις υψηλές συχνότητες των κατακόρυφων διασυνδέσεων διαμέσου του υποστρώματος πυριτίου που χρησιμοποιούνται στα τρισδιάστατα ολοκληρωμένα κυκλώματα αλλά και των βλαβών που συμβαίνουν σε αυτές. Τέλος, αναπτύχθηκε μία νέα μέθοδος εξέτασης των διασυνδέσεων διαμέσου του υποστρώματος πυριτίου, που παρουσιάζει ευρωστία, ανοχή στις διακυμάνσεις, έχει χαμηλό κόστος και ευκολία υλοποίησης.

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Through-Silicon-Via resistive-open defect analysis

Cited by 10 publications

References 4 publications

Timing-aware ATPG for critical paths with multiple TSVs

Timing-aware ATPG for critical paths with multiple TSVs

CoBRA: Low cost compensation of TSV failures in 3D-NoC

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