Through Silicon Via technology using tungsten metallization

Parès, G.; Bresson, N.; Minoret, S.; Lapras, V.; Brianceau, P.; Lugand, J.-F.; Anciant, R.; Sillon, N.

doi:10.1109/icicdt.2011.5783204

Cited by 30 publications

(16 citation statements)

References 10 publications

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“…As can be seen from Figure 1, tungsten has a significantly better matched CTE with silicon than copper has. However, chemical vapor deposited tungsten suffers from high film stress and wafer bow [5], thereby limiting tungsten film thicknesses to few microns [13] meaning that tungsten can only be used in small TSVs [5]. [9,10,11,12,14].…”

Section: Methodsmentioning

confidence: 99%

Wide temperature range through silicon vias made of Invar and spin-on glass for interposers and MEMS

Laakso

Asiatici

Fischer

et al. 2016

2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS)

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Through silicon vias (TSVs) are used e.g. to create electrical connections through MEMS wafers or through silicon interposers used in 2.5D packaging. Currently available technologies do not address situations in which TSVs through unthinned wafers have to withstand large temperature variations. We propose using ferromagnetic Invar metal alloy for this purpose due to its low mismatch in heat induced strain in comparison to silicon. We demonstrate the suitability of a magnetic assembly process for Invar TSV fabrication and the use of spin-on glass as a TSV insulator. We demonstrate TSVs, with contact pads, that tolerate temperature cycling between -50 °C and 190 °C and can withstand elevated temperatures of at least up to 365 °C.

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Section: Methodsmentioning

confidence: 99%

Wide temperature range through silicon vias made of Invar and spin-on glass for interposers and MEMS

Laakso

Asiatici

Fischer

et al. 2016

2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS)

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“…6 For these reasons, doped polysilicon is used in Via-First 7 or tungsten is used in Via-Middle. 8 Unfortunately, these materials have lower electrical conductivity than copper. To be used in 3D IC, copper TSVs have to be metalized in Via-Middle or Via-Last.…”

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confidence: 99%

Electrografted P4VP for High Aspect Ratio Copper TSV Insulation in Via-Last Process Flow

Dequivre

Alam

Brisard

et al. 2016

ECS J. Solid State Sci. Technol.

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Via-Last metallization of High Aspect Ratio Through Silicon Via (HAR TSV) for 3D integration is challenging. Indeed, the formation of a uniform and conformal dielectric to insulate HAR TSVs in Via-Last process flow is difficult to achieve for any physical deposition process. In this study, we present the first reported HAR copper TSVs, insulated by highly conformal electrografted poly-4-vinylpyridine (P4VP) in Via-Last process-flow. As a demonstration, this allowed the metallization of HAR copper TSVs for die-to-die 3D integration of a 22 × 22 photodiode array tier onto a CMOS control electronics ASIC.

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“…Tungsten has been proposed [25,26] as a better CTE-matched alternative to copper (tungsten CTE is 4.42 ppm/…”

Section: Introductionmentioning

confidence: 99%

“…However, high stress in deposited tungsten makes it susceptible to delamination which limits the maximum metal thickness to the order of a few microns and restricts the use of tungsten to small-diameter disk-shaped vias or to ring-shaped (annular) vias [25,26,28]. Thus, for fully metal-filled via holes, the use of tungsten is limited to blind vias or vias in very thin substrates.…”

Section: Introductionmentioning

confidence: 99%

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Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Asiatici

Laakso

Fischer

et al. 2017

J. Microelectromech. Syst.

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Abstract-Through silicon vias (TSVs) are key enablers of 3D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power and a smaller footprint. Copper is the most commonly used conductor to fill TSVs; however, copper has a high thermal expansion mismatch in relation to the silicon substrate. This mismatch results in a large accumulation of thermomechanical stress when TSVs are exposed to high temperatures and/or temperature cycles, potentially resulting in device failure.In this paper, we demonstrate 300 µm long, 7:1 aspect ratio TSVs with Invar as a conductive material. The entire TSV structure can withstand at least 100 thermal cycles from -50• C to 190• C and at least one hour at 365 • C, limited by the experimental setup. This is possible thanks to matching coefficients of thermal expansion (CTE) of the Invar via conductor and of silicon substrate. This results in thermomechanical stresses that are one order of magnitude smaller compared to copper TSV structures with identical geometries, according to finite element modelling. Our TSV structures are thus a promising approach enabling 2.5D and 3D integration platforms for high-temperature and harsh-environment applications.

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Through Silicon Via technology using tungsten metallization

Cited by 30 publications

References 10 publications

Wide temperature range through silicon vias made of Invar and spin-on glass for interposers and MEMS

Wide temperature range through silicon vias made of Invar and spin-on glass for interposers and MEMS

Electrografted P4VP for High Aspect Ratio Copper TSV Insulation in Via-Last Process Flow

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

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