Through silicon vias filled with planarized carbon nanotube bundles

Wang, Teng; Jeppson, Kjell; Olofsson, Niklas; Campbell, Eleanor E. B.; Liu, Johan

doi:10.1088/0957-4484/20/48/485203

Cited by 60 publications

(39 citation statements)

References 35 publications

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“…Additionally, using VA-SWNT films as the electrodes offers two advantages. Firstly, VA-CNT bundles can be potentially useful for via interconnects [30][31][32]. Secondly, since the VA-SWNT films provide a very high surface area, the carrier transport properties may be tunable by adsorbing different molecules.…”

Section: Device Fabricationmentioning

confidence: 99%

Facile fabrication of all-SWNT field-effect transistors

et al. 2011

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Field-effect transistors (FETs) have been fabricated using as-grown single-walled carbon nanotubes (SWNTs) for the channel as well as both source and drain electrodes. The underlying Si substrate was employed as the back-gate electrode. Fabrication consisted of patterned catalyst deposition by surface modification followed by dip-coating and synthesis of SWNTs by alcohol chemical vapor deposition (CVD). The electrodes and channel were grown simultaneously in one CVD process. The resulting FETs exhibited excellent performance, with an I ON /I OFF ratio of 10 6 and a maximum ON-state current (I ON ) exceeding 13 μA. The large I ON is attributed to SWNT bundles connecting the SWNT channel with the SWNT electrodes. Bundling creates a large contact area, which results in a small contact resistance despite the presence of Schottky barriers at metallic-semiconducting interfaces. The approach described here demonstrates a significant step toward the realization of metal-free electronics. KEYWORDSSingle-walled carbon nanotube, field-effect transistor, patterned synthesis, self-assembled monolayer, Schottky barrier, interfacial dipole

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Section: Device Fabricationmentioning

confidence: 99%

Facile fabrication of all-SWNT field-effect transistors

et al. 2011

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“…In [18], a 13 μm thick CNT array on the surface of a free mating substrate exhibiting thermal contact resistance around 15-17 mm 2 K/W was demonstrated. TSVs filled with CNT bundles were fabricated in [19] where a deep reactive ion etching (DRIE) process was used to etch deep vias in silicon. CNTs were then grown on a layer of catalyst at the bottom of the vias by thermal chemical vapor deposition (TCVD) as shown in Fig.…”

Section: Modeling Thermal Effects On Circuit Agingmentioning

confidence: 99%

“…Naturally, the larger the via size, the higher the temperature reduction. CNT bundles with diameters ranging from 20-50 μm have been reported in [19]. Here, we used a 10 μm diameter foreseeing advancements in fabrication techniques and reducing the area overhead.…”

Section: B Effects Of Parameter Variationsmentioning

confidence: 99%

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface

Zhang

Huang

Yang

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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The increasing power consumption of integrated circuits (ICs) enabled by technology scaling requires more efficient heat dissipation solutions to improve overall chip reliability and reduce hotspots. Thermal interface materials (TIMs) are widely employed to improve the thermal conductivity between the chip and the cooling facilities. In recent years, carbon nanotubes (CNTs) have been proposed as a promising TIM due to their superior thermal conductivity. Some CNT-based thermal structures for improving chip heat dissipation have been proposed, and they have demonstrated significant temperature reduction. In this paper, we present an improved CNT TIM design which includes a CNT grid and thermal vias to dissipate heat more efficiently to obtain a more uniform chip thermal profile. We present simulation-based experimental results that indicate a 32% / 25% peak temperature reduction and 48% / 22% improvement in chip reliability for two industrial processor benchmarks, showing the effectiveness of our proposed thermal structure.

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“…Contact resistance due to imperfect contacts is estimated to be cm [7]. The total resistance of a CNT-based TSV can be expressed as (1) where and are the Planck's constant, electron charge, bias voltage and saturation current, respectively. The low-bias MFP in nanotubes can be up to a theoretical 2.8 m [8].…”

mentioning

confidence: 99%

Study on Transmission Characteristics of Carbon Nanotube Through Silicon Via Interconnect

Qian

Zhu

Xia

2014

IEEE Microw. Wireless Compon. Lett.

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In this letter, the Resistance Inductance Capacitance Conductance (RLCG) parameters of carbon nanotube through silicon via (CNT-TSV) are modeled and a transmission line (TL) model is established through ABCD matrix. The impact of their geometrical and material parameters on the TSV transmission characteristics is analyzed over a wideband of frequency using the proposed model. An optimization methodology using air gap insulator is proposed to improve the transmission performance. SPICE results show that a 30.83% reduction in insertion loss and a 40.72% increase in eye open area, respectively.

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Through silicon vias filled with planarized carbon nanotube bundles

Cited by 60 publications

References 35 publications

Facile fabrication of all-SWNT field-effect transistors

Facile fabrication of all-SWNT field-effect transistors

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface

Study on Transmission Characteristics of Carbon Nanotube Through Silicon Via Interconnect

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