Through Wafer Copper Via for Silicon Based SiP Application

Witarsa, D.; Soundara-Pandian, Mohanraj; Yoon, Seung Wook; Kripesh, V.; Weng, Teoh Kum; Nagarajan, Rajamani; Khan, Ovaisullah

doi:10.1109/eptc.2005.1614358

Cited by 11 publications

(7 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When evaluating the elastic stability of the via, the following formula for the radial displacements, u(r), in a thick-walled tube (the problem is known in the theory of elasticity as "Lame problem") subjected to an internal, 0 p , and an external, 1 p pressure (see, e.g., [5]) can be used (Fig.2): r is the inner radius of the disc ("tube"), 1 r is its outer radius, and r is an arbitrary radius of the disc. The formula (1) reflects an assumption that the approximation of the plane stress is applicable.…”

Section: Disc-like Vias: Elastic Stability and Induced Stressesmentioning

confidence: 99%

“…Through-silicon-via (TSV) designs of 3D IC packages have attracted during the last decade considerable attention of packaging technologists and reliability engineers (see, e.g., [1][2][3][4]). The major reliability concern with copper (Cu) vias electroplated in a silicon (Si) wafer has to do with the elevated thermal expansion mismatch stresses in both materials at high temperature conditions.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analytical stress modeling for TSVs in 3D packaging

Suhir

2015

2015 31st Thermal Measurement, Modeling &Amp; Management Symposium (SEMI-THERM)

View full text Add to dashboard Cite

Physically meaningful and easy-to-use analytical solutions are obtained, using analytical modeling and theory-of-elasticity approach, for thermal stresses in typical through-silicon-via (TSV) packages of 3D IC devices. The case when the package is heated up from the room temperature to an elevated temperature is considered. Two extreme cases of the TSV geometry are addressed: disc-like vias, with height/thicknessto-diameter ratio is below 0.25, when plane-stress approximation in the 2D elasticity theory can be used, and rodlike vias, with height-to-diameter ratios above 2.5, when plane strain approximation is applicable. The following objectives have been pursued in the analysis: 1) evaluation of the elastic stability of a disc-like via subjected to the thermal "hoop" pressure caused by the thermal expansion mismatch of the copper (Cu) and silicon (Si) materials; 2) assessment of the thermally induced circumferential stresses in the Si wafer; and 3) the evaluation of the expected relief in the longitudinal (in the TSV axial direction) interfacial shearing stresses due to the application of a ''surrogate'' buffering material, i.e., a material not needed from the standpoint of the functional performance of the design. While the pressure at the Cu/Si interface determines the reliability of the Si material, the longitudinal interfacial shearing stress is critical from the standpoint of the adhesive and cohesive strength of the TSV structure. The numerical example is carried out for different radii of the opening in Si and for the case when Indium is considered as a suitable buffering material. The calculated data indicate that larger openings in Si result in lower pressures on Si and in lower longitudinal interfacial shearing stresses, especially if disc-like vias are employed. The computed data indicate particularly that a 1 m µ thick layer of Indium resultes in about 39% reduction in the induced pressure at the Cu/Si boundary for a disc-like TSV and by about 14% -for a rod-like via. As to the longitudinal interfacial shearing stress, the reductions are even greater: about 69% -for a disc-like TSV and about 41% for a rod-like via. Thus, there seems to be an incentive for employing disc-like TSV designs for lower thermal stresses. In the absence of the strain buffer, the pressure in the disc-like TSV design was only about 58% of the pressure in the rod-like via, and the maximum value of the longitudinal shearing stress was about half the stress in the rod-like TSV. The "bad news" is, however, that while the elastic stability of a rod-like via is never a problem, a disc-like via might buckle under the action of the thermally induced "hoop" stresses, and therefore the elastic stability of a disc-like via should always be evaluated and assured. Our analysis starts, for this reason, with the evaluation of the critical (Euler) pressure for a disc-like TSV.

show abstract

Section: Disc-like Vias: Elastic Stability and Induced Stressesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analytical stress modeling for TSVs in 3D packaging

Suhir

2015

2015 31st Thermal Measurement, Modeling &Amp; Management Symposium (SEMI-THERM)

View full text Add to dashboard Cite

show abstract

“…To isolate the through hole via from the substrate, an insulation layer and a barrier layer is deposited. The insulation layer used is silicon oxide to act as a dielectric isolation layer whereas the barrier layer is silicon nitride that prevents diffusion of the filler metal (copper) into the silicon wafer [7]. The process flow of test vehicle fabrication is illustrate in Fig.2.…”

Section: Carrier Wafer With Cu Via Interconnect Processmentioning

confidence: 99%

Reliability Studies of a Through Via Silicon Stacked Module for 3D Microsystem Packaging

Yoon

Witarsa

Lim

et al.

56th Electronic Components and Technology Conference 2006

Self Cite

View full text Add to dashboard Cite

In this study, two types of reliability tests are studied for silicon stacked module. One is for temperature cycle solder joint reliability. Another is for drop impact test. Test vehicles are fabricated using silicon fabrication processes such as SiO2 deposition, metal deposition, lithography, through via formation, copper plating and dry or wet etching. After flipchip die and silicon substrate fabrication, they are assembled by flipchip bonder. Daisy chains are formed between flipchip dies and each silicon substrates and resistance measurement is carried out with temperature cycle test

show abstract

“…The detailed processes & experiments are discussed in [5]. The silicon carrier fabricated has Under Bump Metallization (UBM) pads for flip chip attach and the same metallization for wire bond interconnection of image sensor die to the silicon carrier.…”

Section: Experimental Details Silicon Carrier Fabricationmentioning

confidence: 99%

“…3D silicon carrier SiP developments have been published earlier [4]. Development of MEMS wafer fab processes like KoH silicon etching, Silicon Deep Reactive Ion Etching (DRIE), deep via Cu plating over the years have enabled manufacturability of silicon carriers/substrates [5,6] which will be the solution to existing problems in packaging like reliability of ultra fine pitch flip chip interconnects, large die, large I/O packaging issues [7] & opens up window for research in 3D miniaturized electronic modules.…”

Section: Introductionmentioning

confidence: 99%

Assembly Technology Development for 3D Silicon Stacked Module for Handheld Products

Ganesh

Lim

Witarsa

et al.

56th Electronic Components and Technology Conference 2006

Self Cite

View full text Add to dashboard Cite

The objective of this consortium research work is to develop a 3D SiP based on silicon platform technology for integrating heterogeneous multifunctional devices for handheld products with imaging application. The developed 3D SiP can be used for signal speed of 2Gbps with designed silicon through via structures and matched transmission lines. The thermal performance of the 3D SiP is optimized for 3 watts heat dissipation by natural convection cooling. This paper focuses on the process development of five key assembly technologies used to fabricate the 3D silicon carrier

show abstract

Through Wafer Copper Via for Silicon Based SiP Application

Cited by 11 publications

References 5 publications

Analytical stress modeling for TSVs in 3D packaging

Analytical stress modeling for TSVs in 3D packaging

Reliability Studies of a Through Via Silicon Stacked Module for 3D Microsystem Packaging

Assembly Technology Development for 3D Silicon Stacked Module for Handheld Products

Contact Info

Product

Resources

About