TID Circuit Simulation in Nanowire FETs and Nanosheet FETs

Abstract

In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

Impact of Rh, Ru, and Pd Leads and Contact Topologies on Performance of WSe2 FETs: A First Comparative Ab Initio Study

“…These V ON values shift slightly due to the insubstantial shifts among the corresponding I D − V G curves, and vice versa. This suggests that WSe 2 /Ru FETs can achieve the most stable circuit operation [ 71 ], outperforming their WSe 2 /Rh and WSe 2 /Pd counterparts.…”

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

“…With continuous minimization of Si integrated circuits (ICs) along the Moore's law, metal oxide semiconductor field effect transistors (MOSFETs) are becoming smaller in size and consuming less in power. [1][2][3][4][5][6][7][8][9] Although three-dimensional (3D) bulk-Si fin field effect transistor (FinFET) has been applied into the IC mass production from 22 nm to 5 nm nodes for a long time, it is becoming more challenging for them to meet the basic requirements of the performance and the power consumption specifications for the next generation ICs. [10][11][12][13][14] Attributed to its high integration density, superiority in the control of short channel effects (SCEs), high performance and large flexibility in circuits design, as well as perfect process compatibility with current FinFET manufacture process, [15][16][17] the vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) FET is believed as one of the most promising solutions to be applied into the mainstream IC manufacture while the technology is shrunk beyond 3nm node.…”