TILOS: A Posynomial Programming Approach to Transistor Sizing

Fishburn, J.P.; Dunlop, A.E.

doi:10.1007/978-1-4615-0292-0_23

Cited by 299 publications

(225 citation statements)

References 4 publications

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“…The influential book by Sutherland et al (1999) is almost entirely devoted to the sizing problem. Sizing of digital circuits is a wellresearched field, with hundreds of papers on the topic; see, e.g., the articles by Fishburn and Dunlop (1985), Passy (1998), Chen et al (2004), Kim et al (2004), Kasamsetty et al (2000), Sapatnekar (1996), and Sapatnekar et al (1993) and the references therein.…”

Section: Digital Circuit Sizingmentioning

confidence: 99%

“…In addition, other GP-compatible constraints can be added, e.g., a limit on the energy loss, or signal rise times. Wire sizing using Elmore delay goes back to Fishburn and Dunlop (1985); for some more recent work on wire (and device) sizing via Elmore delay, see, e.g., Shyu et al (1988), Sapatnekar et al (1993), and Sapatnekar (1996). The state of the art in interconnect wire sizing is well summarized in the survey papers , Sylvester and Hu (2001), and Ho et al (2001).…”

Section: 22mentioning

confidence: 99%

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Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Digital Circuit Sizingmentioning

confidence: 99%

Section: 22mentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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“…where, m is the number of nodes in the circuit graph, K l is a constant coefficient of the l th monomial term, which can be derived 1 The Elmore delay model is used for simplicity. Alternatively, generalized posynomial delay models [3], which have a higher accuracy, can be used for the GP formulation.…”

Section: Preliminaries 21 Conventional Gate Sizing As a Gpmentioning

confidence: 99%

“…The traditional gate sizing methodologies [1], [2] use Elmore delay based posynomial delay constraints to formulate the problem as a Geometric Program (GP). The use of posynomial delay models for the gate sizing problem enables the use of efficient convex optimization tools to solve the problem [3].…”

Section: Introductionmentioning

confidence: 99%

Robust gate sizing by geometric programming

Singh¹,

Nookala²,

Luo³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a Geometric Program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over the traditional deterministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area, has fewer timing violations.

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“…Many approaches have been proposed [1][2][3][4][5][6][7][8]. Among them, a frequently used mathematical optimization technique for gate sizing is linear programming.…”

Section: Introductionmentioning

confidence: 99%