This paper investigates the problem of improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops. Through the use of a model to detect clocking hazards, two linear programs are investigated: 1) Minimize the clock period, while avoiding clock hazards. 2) For a given period, maximize the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.

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Euler's differential equation of the calculus of variations is used to determine the shape of a distributed-RC wire that minimizes Elmore delay. In two dimensions the optimal shape is an exponential taper. In three dimensions the optimal shape is a frustum of a cone. Ri R2 RtlAbstruct-Voltage collapse has been commonly associated with insufficient reactive power support. Steady state studies have related reactive power generation limitations to the sudden onset of voltage instability. This paper extends this approach to the dynamic case. The relationship between the dynamic models and steady state behavior is established. The dynamic model is then used to investigate the sudden change in system stability when the maximum excitation limit is reached. Several illustrative examples are analyzed. Corrective actions are proposed which will move the physical system away from the region of instability.

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