Shaping a distributed-RC line to minimize Elmore delay

Fishburn, J.P.; Schevon, Catherine A.

doi:10.1109/81.481198

Cited by 68 publications

(39 citation statements)

References 10 publications

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“…There is a large literature on Elmore delay and related topics; see, e.g., Alpert et al (2001a), Kashyap et al (2004), Kahng and Muddu (1997), Gupta et al (1997), Schevon (1995), andHorowitz (1984). Rubenstein et al (1983) published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees.…”

Section: Rc Tree Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Rc Tree Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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“…When the wire width w varies in the range of £ w lo ¥ w hi¦ , we need to find a wire shaping function w § x such that the delay from the virtual driver R to the sink is maximized or minimized. The minimum delay wire shaping function for a path without branch loads is solved in [8,3]. An iterative wire shaping algorithm is provided in [4] to minimize a weighted sum of sink delays in a routing tree.…”

Section: Problem Analysismentioning

confidence: 99%

“…Our proposed technique is based on the observation that estimating the worst case skew due to wire width variation is closely related to the non-uniform wire sizing problem in physical optimizations. The minimum delay non-uniform wire sizing problem for a 2-pin wire(single load path) has been solved in [8,3]. We derive the maximum wire shaping function for both single load path and multi-pin trees.…”

Section: Introductionmentioning

confidence: 99%

“…Previously, a more general version of this problem was solved through an iterative algorithm [4]. Similar to the works of [8,3,4], we employ Elmore delay model for our derivations because of its high fidelity and ease of computation. Besides the bound, we discovered that the bound for skew between two clock sinks depends on their common upstream path, even though the skew between them is independent of the common path.…”

Section: Introductionmentioning

confidence: 99%

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Analytical bound for unwanted clock skew due to wire width variation

Rajaram

Liu

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck preventing further improvement on clock frequency. Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, we establish an analytical bound for the unwanted skew due to wire width variation which is the dominating factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter and computationally faster than similar existing approach.

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“…Wire sizing techniques (both continuous and discrete) for minimizing delay have been widely studied [4], [5]. Perhaps, one of the most sophisticated approaches to minimize wire delay is to adopt simultaneous buffer insertion and uniform wire sizing scheme.…”

Section: Introductionmentioning

confidence: 99%

Interconnect delay minimization using a novel pre-mid-post buffer strategy

Prasad

Desai

16th International Conference on VLSI Design, 2003. Proceedings.

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We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.

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Shaping a distributed-RC line to minimize Elmore delay

Cited by 68 publications

References 10 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Analytical bound for unwanted clock skew due to wire width variation

Interconnect delay minimization using a novel pre-mid-post buffer strategy

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