Clock skew optimization

Abstract

This paper investigates the problem of improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops. Through the use of a model to detect clocking hazards, two linear programs are investigated: 1) Minimize the clock period, while avoiding clock hazards. 2) For a given period, maximize the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.

Clock period minimization of non-zero clock skew circuits

“…Then, our algorithm moves to the procedure Delay_Insertion. We find that T PD3,4(min) is critical in G cg (G MIN (1) ,P MIN(1) ). Since T PD3,4(max) =6 tu and T PD3,4(min) =1 tu, we have p 3,4 =5 tu in G INS (1) .…”

“…We find that T PD3,4(min) is critical in G cg (G MIN (1) ,P MIN(1) ). Since T PD3,4(max) =6 tu and T PD3,4(min) =1 tu, we have p 3,4 =5 tu in G INS (1) . By applying OCSS to G INS(1) , we have S INS(1) =(0,0,0.5,1,2.5) and P INS(1) =4.5 tu.…”

“…By applying OCSS to G INS(1) , we have S INS(1) =(0,0,0.5,1,2.5) and P INS(1) =4.5 tu. The constraint graph G cg (G INS (1) ,P INS (1) ) is given in Figure 7.…”

“…Previous works [3,4] have tried to improve the optimal clock skew scheduling by combining with retiming transformation. However, retiming transformation is likely to have the following effects in the design flow: (1) an extra circuitry may be needed for initial states; (2) the forward retiming may increase the number of registers; and (3) verification issues. This paper investigates the clock period minimization problem from a different standpoint.…”

“…Although the optimal clock skew scheduling [1,2] can enhance the circuit performance, it does not achieve the lower bound of the clock period. In fact, the maximum delay-to-register ratio of the cycles in the circuit gives a lower bound of the clock period.…”