Closing the Gap Between ASIC &Amp; Custom
DOI: 10.1007/0-306-47823-4_8
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Useful-Skew Clock Synthesis Boosts ASIC Performance

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Cited by 3 publications
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“…A usual approach is to bound or minimize the global clock skew. Global clock skew is the largest skew value among all pairs of flip-flops within a clock domain, which is simply the difference in arrival times between the earliest and latest arriving clock signals [6].…”
Section: Useful Skew-based Clock Tree Generationmentioning
confidence: 99%
“…A usual approach is to bound or minimize the global clock skew. Global clock skew is the largest skew value among all pairs of flip-flops within a clock domain, which is simply the difference in arrival times between the earliest and latest arriving clock signals [6].…”
Section: Useful Skew-based Clock Tree Generationmentioning
confidence: 99%