Optimization-based transistor sizing

Shyu, J.-M.; Sangiovanni‐Vincentelli, Alberto; Fishburn, J.P.; Dunlop, A.E.

doi:10.1109/4.1000

Cited by 143 publications

(45 citation statements)

References 5 publications

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“…The problem of continuous sizing, in which transistor sizes are allowed to vary continuously between a minimum size and a maximum size, has been tackled by several researchers [1][2][3][4]. The problem is most often posed as a nonlinear optimization problem, with nonlinear programming techniques used to arrive at the solution.…”

Section: G a Te S Izin G P Ro B Lemmentioning

confidence: 99%

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Timing and area optimization for standard-cell VLSI circuit design

Chuang

Sapatnekar²,

Hajj

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: G a Te S Izin G P Ro B Lemmentioning

confidence: 99%

“…where 2/i, 2/2, • • •, Vf is the sizes of the cells to which G fans out; a and ¡3 are related to transistor gate terminal area and perimeter capacitances [3]. Thus, the delay function D(x) of G is a function i<Y<?…”

Section: F Orm U Lation O F D E La Y C O N Stra In Tsmentioning

confidence: 99%

Timing and area optimization for standard-cell VLSI circuit design

Chuang

Sapatnekar²,

Hajj

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In addition, other GP-compatible constraints can be added, e.g., a limit on the energy loss, or signal rise times. Wire sizing using Elmore delay goes back to Fishburn and Dunlop (1985); for some more recent work on wire (and device) sizing via Elmore delay, see, e.g., Shyu et al (1988), Sapatnekar et al (1993), and Sapatnekar (1996). The state of the art in interconnect wire sizing is well summarized in the survey papers , Sylvester and Hu (2001), and Ho et al (2001).…”

Section: 22mentioning

confidence: 99%

“…Since then many digital circuit design problems have been formulated as GPs or related problems. Work on gate and device sizing (the main topics of this paper) can be found in, e.g., Chu and Wong (2001b), Passy (1998), Cong and He (1999), Kasamsetty et al (2000), Matson and Glasser (1986), Pattanaik et al (2003), Shyu et al (1988), Sancheti and Sapatnekar (1996), Sapatnekar and Chuang (2000), and Sapatnekar et al (1993). These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models.…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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“…In its search for the optimum, TILOS increases the size of the critical transistor by a fixed value during each iteration [5]. But, there call arise situations where the sizes of the transistors along a critical path need t o be reduced; TILOS is not very well suited t o handle such cases [7]. Any automated optimization program works in close conjunction with a timing-analysis software.…”

Section: Introductionmentioning

confidence: 99%

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Dutta

Nag

Roy

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

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This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gatelevel functio~nal models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. ASAP considers the performailce improvement of VLSI CMOS circuits by optimally sizing the transistors on the first N critical paths. The global picture of the circuit is considered by taking into account the effects that the transi.stor size changes of one path have on the others. The optimization technique in our sizing tool is based on simulated annealing and couples accurate delay modeling with power and area optimization. The combinatorial minimization of the objective function relies on analytical models that can accurately evaluate the delay, the power and the area of a gate. ASAP has been implemented in C on an Apollo 400 workstation with encouraging results.

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Optimization-based transistor sizing

Cited by 143 publications

References 5 publications

Timing and area optimization for standard-cell VLSI circuit design

Timing and area optimization for standard-cell VLSI circuit design

Digital Circuit Optimization via Geometric Programming

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

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