Timing and area optimization for standard-cell VLSI circuit design

Chuang, Weitong; Sapatnekar, Sachin S.; Hajj, I.N.

doi:10.1109/43.365122

Cited by 29 publications

(1 citation statement)

References 28 publications

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“…Previous approaches such as Sleepy Stack Technique [4], Input Vector Control (IVC) [6] and customised RTL designs [7] techniques have each had their individual drawbacks of high delay and area overheads, additional hardware units or low impact for deep sub-micron regimes (<20% power reduction). Automated sizing approaches using Linear Programming [8], Convex Optimization [9], Multi-Objective Optimization [10] and use of Lagrangian Relaxation [11] had all adopted gate sizing wherein all the transistors in a standard cell were scaled by the same factor. This top-down approach is highly circuit specific and the rise in number of variables for larger circuits makes the process highly complex.…”

Section: Related Workmentioning

confidence: 99%

Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

Saha

Ahmed

Kalluru

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55 o C to 125 o C) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.

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