Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology

Abstract

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-ofthe-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM). v DEDICATION I would like to dedicate this thesis to my parents. My father who is my role model in the whole aspects of my life. He is the reason I continued my education to make him lofty and proud as he coveted, and my mother who always supports me with her everlasting love. My parents offered unwavering encouragement for the endeavors I have pursued. Their staunch supports, love, and inspiration have given me valor to attain this degree. They made my life be in debt to them. I would also like to dedicate my works and achievements to my nephews, Parham and Amirpasha that they have always been missed. Love all of you to the moon and back. vi ACKNOWLEDGEMENTS "Think for your lord's gratification, be intellectual and truthful-Ferdowsi" First, I would like to express my gratefulness to my thesis adviser, Professor Sotoudeh Hamedi-Hagh. This thesis would have not been accomplished without his dedication, kindness, and his perpetual support. I would like to thank Professor Hamedi-Hagh for providing me the access to Radio Frequency Integrated Circuits (RFIC) lab and Cadence software. I am inclined to thank Professor Thuy Le, the graduate adviser of San Jose State University, for his continuous support during the hardship times. I would like to show my gratitude to all my colleagues, Rahul Sreekumar, Andrew Chen, Daniel Mazidi, Priyanka Agrawal, and Fleura Hajilou in Analog Mixed-Signal (AMS) center and RFIC lab for creating friendly atmosphere along with treasured discussions. Eventually, I should express my appreciativeness to my brothers, Habib, Hamed, and Hamid for their unconditional supports, and all the people who made the privations facilitated for me in this path. vii