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This paper describes a current steering 8-bit DAC architecture for low power and high-speed assistance in AI networks. This design is most suitable for 5G and next-generation high-speed communication systems on chip (SoCs). This DAC keeps a constant load current and leads to faster operations in wideband portable device applications. The design is based on weighted current transmission through current mirrors wherein current reduces from MSB to LSB continuously. By choosing a low current for LSB, the power dissipation reduces. Power and area are also reduced by using a 2-bit binary to thermometer decoder. The DAC's integral nonlinearity (INL) and differential nonlinearity (DNL) are found to be within 0.4 and 0.9 LSB, respectively. The DAC's highest operating speed is 1GHz, with a power dissipation of around 24.2 mW with the supply voltage of 1.8v using 180nm CMOS technology.

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.