Time constrained allocation and assignment techniques for high throughput signal processing

Geurts, Werner; Catthoor, Francky; Man, H. De

doi:10.1109/dac.1992.227849

Cited by 20 publications

(11 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This task is being automated in the CATHEDRAL 3 compiler [24]. Eventually each datapath is represented by a netlist of locally interconnected hardware building blocks.…”

Section: Results and Conclusionmentioning

confidence: 99%

“…Although tuned to real-time signal processing problems, the backbone is highly independent from the architectural styles and the application domains supported by the compilers which are integrated on top of it. Currently, the backbone is in use by several high-level synthesis systems: CATHEDRAL 2ND, CATHEDRAL 3 [24] and CBC [14]. Throughout the synthesis process, any design can be consistently represented using two linked information models: a signal-flow graph model to represent the algorithm under synthesis, and a netlist model to represent the architecture.…”

Section: Design Representation and The Data Model Backbonementioning

confidence: 99%

See 1 more Smart Citation

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Goossens

Lanneer

Pauwels

et al. 1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Abstract. Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

show abstract

“…This task is being automated in the CATHEDRAL 3 compiler [24]. Eventually each datapath is represented by a netlist of locally interconnected hardware building blocks.…”

Section: Results and Conclusionmentioning

confidence: 99%

Section: Design Representation and The Data Model Backbonementioning

confidence: 99%

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Goossens

Lanneer

Pauwels

et al. 1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

show abstract

“…Some attempts have been made to deal with this problem but there is no clear solution yet. In [2][3] [4], the problem of generating hierarchical structures was tackled, but the authors did not focus on productivity issues (as possible component reusability) arisen from a hierarchical strategy. Even though, their approaches were capable of producing hierarchical structures containing some optimisation, via restricted rules in partitioning of data-flow [2] or control-flow [3][4] graphs derived from plain algorithmic descriptions.…”

Section: Introductionmentioning

confidence: 99%

“…In [2][3] [4], the problem of generating hierarchical structures was tackled, but the authors did not focus on productivity issues (as possible component reusability) arisen from a hierarchical strategy. Even though, their approaches were capable of producing hierarchical structures containing some optimisation, via restricted rules in partitioning of data-flow [2] or control-flow [3][4] graphs derived from plain algorithmic descriptions. In [5], it is shown a structured methodology capable of dealing with hierarchical algorithmie designs using a HLS system, but they did not show any automatie means for producing optimised implementations.…”

Section: Introductionmentioning

confidence: 99%

Architectural Transformations for Hierarchical Algorithmic Descriptions

Teruya

Strum

Chau

2000

VLSI: Systems on a Chip

View full text Add to dashboard Cite

Abstract:The use of hierarchy on writing algorithmic descriptions of digital systems allows the implementation of more complex designs since it increases designer's productivity by introducing important features such as modularity, encapsulation and reusability. We are particularly interested in the problem of generating an optimal register transfer logic structure from a hierarchical algorithmic description. It is relatively straightforward to use High Level Synthesis (HLS) tools for producing an implementation from hierarchical algorithmic descriptions; each algorithmic partition is implemented separately and then linked in a following step. In general, the results are sub-optimal due to the large gap existing between the specification and implementation. In this article, we detail a simple architectural model for hierarchical algorithmic descriptions and a set of architectural transformations, which are the core of a methodology, Recursive High Level Synthesis (RHLS), aimed to optimise hierarchical implementations. The transformations are used to reshape the architecture of pre-existing hierarchical algorithmic descriptions in order to provide better synthesis results from HLS. We have implemented a suitable data structure and a set of transformations and tested them over a set of hierarchical algorithmic examples.

show abstract

“…applicable for arbitrary hierarchical signal/control flow graphs with loop, function and condition blocks [4]. Still, in order to make the notations less heavy, we will restrict the formulation to the sufficiently representative case of a set of nested iterative constructs where each iterative block contains exactly 1 iterative subblock, in addition to a number of other conditional blocks and/or statements.…”

Section: : Methodology For Matched Throughput In Case Of Irregular Lmentioning

confidence: 99%

Loop transformation methodology for fixed-rate video, image and telecom processing applications

Catthoor

Geurts

Man

Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94)

Self Cite

View full text Add to dashboard Cite

Many real-time signal pmessing applications are dominated by iterative loop constructs which exhibit a large amount of parallelism. In general, a realisation matched to the required mte of these applications exploits only a relatively small part of the parallelism available in the algorithm. This paper addresses the important problem of selecting the appropriate algorithmic-level decisions, in particular loop manipulations and the like, to arrive at an area-optimized specification for use in register-transfer level synthesis tools. One of the crucial cost factors in this optimisation is memory storage related. A n effective model and methodology are proposed to derive an optimized architecture with fully matched throughput, while avoiding a full traversal of the large search space. The effectiveness of our apprwch is substantiated with seveml realistic test cases. 1: IntroductionMany real-time signal processing (RSP) applications in video, image, speech and telecom processing are dominated by iterative loop constructs which exhibit a large amount of parallelism. Still, the loop organisation is not regular for most realistic algorithms in this target domain [l, 251. In general, a ked-rate realisation of these applications exploits only a relatively small part of the available parallelism. Hence, the main problem is not only to derive upper bounds on the amount of parallelism and on the achievable throughput [2, 21, 23, 16, 221, but especially to select a loop organisation matched to the required throughput. This important problem necessitates the traversal of a very large search space and has not been well researched yet. Only very recently, some research has addressed part of this problem. It is oriented mostly to good estimators to guide the search for feasible solutions under certain restrictions, combined with a hierarchical design space exploration This paper addresses the problem of selecting the appropriate loop manipulations on the initial behavioural description, to arrive at an area-optimized specification with matched throughput. The latter can then be used as input for register-transfer level synthesis tools, i.e. detailed allocation, assignment and scheduling. The cost function to steer these loop transformations should not only include the data-path area but it has to incorporates also the crucial foreground and background memory. Indeed, these storage related factors can be quite dominant over the other costs in multi-dimensional signal processing as in video, image and speech processing [I, 251. Up to now, they have been mostly neglected in the conventional high-level synthesis approaches. Also in the array synthesis community (see most P21. *Professor at the Katholieke Universiteit Leuven'This research has been partly sponsored by the E.C. projects ESPRIT-2260 (SPRITE) and HCM-ERBCHRXCT930382 (Vision algorithms and optical computer architectures).

show abstract

Time constrained allocation and assignment techniques for high throughput signal processing

Cited by 20 publications

References 5 publications

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Architectural Transformations for Hierarchical Algorithmic Descriptions

Loop transformation methodology for fixed-rate video, image and telecom processing applications

Contact Info

Product

Resources

About