Time-decoupled parallel SystemC simulation

Weinstock, Jan Henrik; Schumacher, Christoph; Leupers, Rainer; Ascheid, Gerd; Tosoratto, Laura

doi:10.7873/date.2014.204

Cited by 9 publications

(3 citation statements)

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“…In [10,33] a parallel SystemC simulator implementation called SCope is proposed. The idea is to run different processor models on separate simulator instances.…”

Section: Distributed Time/relaxing Synchronizationsmentioning

confidence: 99%

“…Parallel discrete event simulation (PDES) has been exploited, first, with a conservative approach [5][6][7][8], where all the time constraints are strictly fulfilled. Then with a more optimistic approach, by relaxing the synchronization with a time quantum [9,10]. Optimistic approaches may need a rollback mechanism in case the simulation went through an invalid path.…”

Section: Introductionmentioning

confidence: 99%

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Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

2016

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Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level.

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“…In [10,33] a parallel SystemC simulator implementation called SCope is proposed. The idea is to run different processor models on separate simulator instances.…”

Section: Distributed Time/relaxing Synchronizationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

2016

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“…It provides an event driven simulation interface using processes to describe concurrent hardware activity. While the reference SystemC implementation (OSCI ) operates strictly sequential, recently proposed simulation kernels such as SCope [7] are capable of executing multiple SystemC processes concurrently. SCope operates in a time-decoupled fashion by allowing individual processes to simulate ahead in time to avoid synchronization overhead.…”

Section: Introductionmentioning

confidence: 99%

Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator

Weinstock

Leupers

Ascheid

2015

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems

Self Cite

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The growing complexity of modern embedded systems poses a challenge to designers of virtual platforms, as the increasing number of processors causes simulation speed to degrade. To remain viable as design tools, virtual platforms must use highly abstracted modeling levels or deploy parallel simulation technologies to keep performance up. With multi-core PC workstations being widely available today, parallel simulation seems an attractive solution. However, the introduction of concurrency into a virtual platform simulator complicates the construction of synchronization mechanisms of the simulated models. Therefore, this work presents a modeling approach for concurrent LL/SC based on SystemC/TLM. This facilitated the construction of a parallel simulator for a quad-core OpenRISC based system, gaining a performance speedup of 3.4× over a regular sequential simulator.

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Virtual Hardware-in-the-Loop Co-simulation for Multi-domain Automotive Systems via the Functional Mock-Up Interface

Bücs

Murillo

Korotcenko

et al. 2016

Lecture Notes in Electrical Engineering

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Time-decoupled parallel SystemC simulation

Cited by 9 publications

References 0 publications

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator

Virtual Hardware-in-the-Loop Co-simulation for Multi-domain Automotive Systems via the Functional Mock-Up Interface

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