Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Matocha, Kevin; Dunne, Greg; Soloviev, Stanislav I.; Beaupre, Richard

doi:10.1109/ted.2008.926595

Cited by 77 publications

(68 citation statements)

References 21 publications

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“…The reliability of gate oxides is often studied by performing TDDB measurements on MOS devices, which consist of measuring the mean time to failure while stressing the devices at an elevated electric field [3]. For SiO 2 on 4H-SiC, TDDB measurements on MOS devices usually result in reliabilities inferior to the intrinsic ones expected for ideal SiO 2 [3,8].…”

Section: Resultsmentioning

confidence: 99%

“…For SiO 2 on 4H-SiC, TDDB measurements on MOS devices usually result in reliabilities inferior to the intrinsic ones expected for ideal SiO 2 [3,8]. Possible causes of poor gate oxide reliability are considered to be crystalline defects reaching the oxide/semiconductor interface, carbon impurities in thermally grown SiO 2 , or surface roughness.…”

Section: Resultsmentioning

confidence: 99%

“…3C-SiC is predicted to result in better MOSFET channel mobility than the hexagonal (α) SiC polytypes, since the lower bandgap means that the near interface traps (NITs) at the SiO 2 /SiC interface are energetically located above the conduction band minima of this polytype and should therefore not reduce the mobility values [1,2]. Moreover, α-SiC MOS devices have been found to be less reliable than their Si counterparts, which is attributable to the smaller conduction band offset (∆E C ) at the semiconductor/SiO 2 interface (∆E C-4H-SiC ≈ 2.7 eV compared to ∆E C-Si ≈ 3.15 eV) [3]. This means that less energy is required to cause electron injection from the semiconductor into the oxide, resulting in faster accumulation of defects.…”

Section: Impact Of Morphological Features On the Dielectric Breakdownmentioning

confidence: 99%

“…However, the reliability and premature BD generation mechanisms in thermal oxides grown on 3C-SiC has not been addressed. In addition to the intrinsic properties of the dielectric, the BD event is controlled by defects on the semiconductor surface, the conduction band offset at the semiconductor/SiO 2 interface, and oxidation and post oxidation conditions [3,5]. The nature of the defects, the conduction band offset and the optimal oxidation and post oxidation conditions [6] are different for 3C-SiC compared to the better studied 4H polytype.…”

Section: Impact Of Morphological Features On the Dielectric Breakdownmentioning

confidence: 99%

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Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

Eriksson¹,

Roccaforte²,

Weng³

et al. 2010

AIP Conference Proceedings

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Impact Of Morphological Features On the Dielectric Breakdownmentioning

confidence: 99%

Section: Impact Of Morphological Features On the Dielectric Breakdownmentioning

confidence: 99%

See 2 more Smart Citations

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

Eriksson¹,

Roccaforte²,

Weng³

et al. 2010

AIP Conference Proceedings

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On-state current stress-induced subthreshold I–V instability in SiC DMOSFETs

Lelis

Green

Habersat

et al. 2009

2009 International Semiconductor Device Research Symposium

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The reliability of SiC DMOSFETs has been studied in the past several years, including gate oxide reliability with time-dependent dielectric breakdown measurements [1][2], and threshold voltage stability with gate-bias and On-state current stress measurements [2][3][4]. For example, it has been reported that gate-bias stressing causes a time-dependent shift in threshold voltage, and that an On-state current stress causes a slightly larger thresholdvoltage instability [4]. Furthermore, it has been observed that an increase in Off-state leakage current can occur at high temperatures but which can be reduced with the application of a negative gate-bias, indicating an increase in subthreshold-voltage leakage current [5]. It has also been reported that the bias-stress induced threshold-voltage instability increases at increasing temperatures for some SiC MOSFET sample sets [6]. The subthreshold portion of the current-voltage (I-V) characteristic is what affects theOff-state leakage current, so it is particularly important to determine the effect of bias or current stress on the subthreshold I-V characteristics. Fig. 1 shows the subthreshold I-V characteristics of a 20-A SiC MOSFET, fairly representative of the state of the art, which has been subjected to gate-bias stress of both positive and negative bias. The subthreshold slopes have been found by fitting to the curves. The curves following an initial 10-s bias stress are in gray and the slope lines are dashed. The curves following a 10,000-s bias stress are in black and the slope lines are solid. The longer bias stress causes a noticeable shift to the right following positive bias stress, thus increasing the magnitude of the I-V instability. It is interesting to note that the subthreshold slope following negative gate-bias stress is more stretched out, which is likely due to oxide traps filling during the measurement [7]. Fig. 2 shows a similar instability in the I-V curves due to gate-bias stressing, but this time immediately following an On-state current stress of the same time duration. Clearly, the subthreshold slope following a negative gate-bias stress is now more stretched out, especially after the longer almost 10,000-s stress and the I-V curves move further apart for the longer bias (and On-state) stress. This result suggests that the On-state current stress creates additional active nearinterfacial charge traps.These results suggest that not only does On-state stressing of a SiC DMOSFET increase the threshold-voltage instability due to increased charge trapping [4], but that the subthreshold-voltage characteristic is shifted permanently to the left and is degraded such that there is an increased chance that Off-state leakage current could increase, especially at elevated operating temperatures -at the very least that the margin has been noticeably reduced. These measurements were all performed at 30°C, although self-heating during the On-state stress raised the temperature of the device under test to around 70°C. It still remains to compare the effect of t...

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Analysis of Dislocation Structures in 4H‐SiC by Synchrotron X‐Ray Topography

Matsuhata¹,

Yamaguchi²,

Sekiguchi

et al. 2016

Electrical Engineering Japan

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SUMMARY Current 4H‐SiC wafers contain certain amount of dislocations, stacking faults, and other lattice‐defects. These defect structures evolve during various processes for power device fabrication. It is very important to examine evolutions of dislocation structures during power device processes, as well as the effect of dislocations on performances of fabricated power devices. Since lattice defects can be observed at only subsurface regions selectively by Berg–Barrett X‐ray topography, we have applied this useful observation technique to 4H‐SiC technology to solve various technological issues. Appearances of scratch‐like surface morphology after epi‐film growth on very flat substrate surface by chemomechanically polish were examined by this technique, and the mechanism was discussed. Analyses of dislocation structure evolutions during epi‐film growth and also basal‐plane dislocation glide by recombination of electrons and holes were discussed. Effects of threading‐screw dislocations on reliability of MOS structures and on current leakage in pn‐junction under reversed bias condition were investigated and discussed. Various important suggestions for 4H‐Sic industries were obtained.

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Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Cited by 77 publications

References 21 publications

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

On-state current stress-induced subthreshold I–V instability in SiC DMOSFETs

Analysis of Dislocation Structures in 4H‐SiC by Synchrotron X‐Ray Topography

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Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Cited by 77 publications

References 21 publications

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

On-state current stress-induced subthreshold I&#x2013;V instability in SiC DMOSFETs

Analysis of Dislocation Structures in 4H‐SiC by Synchrotron X‐Ray Topography

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On-state current stress-induced subthreshold I–V instability in SiC DMOSFETs