Time redundancy for error detecting neural networks

Abstract

Concurrent error detection at an architectural level is ofren a basic requirement to achieve fault tolerance in neural networks Jbr mission-critical applications. Time redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic arle analyzed as low-cost approaches to concurrent error detection. Different architectural approaches for the neural network design are considered to match the implementation constraints.0-7803-2466-8/95 $4.00 01995 IHEE 111