Time-shared TMR for fault-tolerant CORDIC processors

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.

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Time-shared TMR for fault-tolerant CORDIC processors

Cited by 2 publications

References 13 publications

A new radiation-hardened architecture for holographic memory address calculation

A new radiation-hardened architecture for holographic memory address calculation

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

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