Time-to-Digital Converter with Pseudo-Segmented Delay Line

Kwiatkowski, P.; Szplet, R.

doi:10.1109/i2mtc.2019.8826927

Cited by 5 publications

(2 citation statements)

References 22 publications

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“…However, in modern TCL solutions, especially implemented in FPGA devices, it is hard to achieve strictly this code [11,13]. Looking carefully at different tapped delay line architectures used in TDCs [25] one may conclude that it is important to obtain a possibly high number of output codes whose occurrence is evenly spread in the converter measurement range. Such reasoning has led to the creation of, e.g., the BOUNCE architecture [39].…”

Section: Dsp Slice Configurationmentioning

confidence: 99%

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Metrology and Measurement Systems

Kwiatkowski¹

2019

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The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.

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Section: Dsp Slice Configurationmentioning

confidence: 99%

“…In the literature a vast amount of works related to FPGA TDC implementation can be found in recent years [5,[8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. The vital element of most high-performance TDCs are picosecondresolution tapped delay lines [26].…”

Section: Introductionmentioning

confidence: 99%