Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores

Yan, Li; Suhendra, Vivy; Liang, Yun; Mitra, Tulika; Roychoudhury, Abhik

doi:10.1109/rtss.2009.32

Cited by 104 publications

(55 citation statements)

References 19 publications

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“…In [20], a dual-core processor with a shared L2 cache model is considered. In [13], task lifetime information is computed and utilized to refine possible interferences. In [7], a method for identifying and bypassing the static single usage memory blocks so as to reduce the number of interferences is proposed.…”

Section: Discussionmentioning

confidence: 99%

Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidation of memory blocks at higher cache levels. In order to ensure safety, analysis of cache hierarchies with inclusive caches for worst-case execution time (WCET) estimation is typically based on conservative decisions. Thus, the estimation may not be tight. In order to tighten the estimation, this paper proposes an approach that can more precisely analyze the behavior of a cache hierarchy maintaining the inclusion property. We illustrate the approach in the context of multi-level instruction caches. The approach first analyzes all the inclusive caches in the hierarchy in a bottom-up direction, and then analyzes the remaining non-inclusive caches in a top-down direction. In order to capture the inclusion victims and their effects, we also propose a concept of aging barrier and integrate it with the traditional must and persistence analyses to safely slow down their aging process so as to derive more precise analyses. We evaluate the proposed approach on a set of benchmarks and the evaluation reveals that the estimations are tightened.

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Section: Discussionmentioning

confidence: 99%

Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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“…all accesses are hits, and (ii) data references from different threads will not interfere with each other in the shared L2 cache. Li et al (2009a) proposed a method to estimate the worst-case response time of concurrent programs running on multicores with shared L2 caches, assuming setassociative instruction caches using the LRU replacement policy. Their work was later extended by Chattopadhyay et al (2010) by adding a TDMA bus analysis technique to bound the memory access delay.…”

Section: Related Work With a Focus On Shared Caches And Scratchpadsmentioning

confidence: 99%

“…Among them, the approach proposed by Li et al (2009b) analyzes the worst-case cache access scenario of parallelized applications modeled by Message Sequence Graphs. The approach suffers from a very high time-complexity and assumes that the cache access behaviors are known and finite.…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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“…One solution to this predicament might be to use an analysis approach that, for all the tasks that may run in parallel, studies statically, at a very fine grain of detail on an abstract model of the processor, the accesses that they may make to hardware shared resources and how they might contend with one another [18], [16]. This technique may lead to determine ETB that are considerably tighter than what we can arrive at, but at the cost of a much more onerous and complex effort, which trades time composability for tightness, since its results can only apply to a given task configuration that cannot be varied without invalidating the analysis results.…”

Section: Related Workmentioning

confidence: 99%

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Fernández

Abella

Quiñones

et al. 2015

2015 IEEE 18th International Symposium on Real-Time Distributed Computing

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Abstract-The timing verification of real-time singlecore systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes of the individual tasks, including the ETB, are studied from the system level perspective. The transition between those two steps involves accounting for the interference effects that arise when tasks contend for access to shared resource. The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress while actually holding the CPU, which are very difficult to tightly capture by simply inflating the tasks' ETB. In this paper we show how contention on access to hardware shared resources creates a circular dependence between the determination of tasks' ETB and their scheduling at run time. To help loosen this knot we present an approach that acknowledges different flavors of time composability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two real processor boards used in the space domain.

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Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores

Cited by 104 publications

References 19 publications

Top-down and bottom-up multi-level cache analysis for WCET estimation

Top-down and bottom-up multi-level cache analysis for WCET estimation

An extensible framework for multicore response time analysis

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

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