2020 30th International Conference on Field-Programmable Logic and Applications (FPL) 2020
DOI: 10.1109/fpl50879.2020.00035
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Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

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“…In this paper, we investigate the impact of dedicated placement on performance of architectures with direct connections between LUTs. Its original version appeared at the 30th International Conference on Field-Programmable Logic and Applications (FPL) [27] and introduced a dedicated detailed placement algorithm targeting FPGA architectures with such direct connections, combining iterative solving of Linear Programs (LPs) to select nodes that should be moved from their original positions determined by a general placer oblivious of the direct connections, and Integer Linear Programs (ILPs) to appropriately position them. The main technical novelty that this extended version of the paper brings is a greatly simpliied and improved main algorithm that orchestrates the construction and solving of diferent LPs and ILPs.…”
Section: Introductionmentioning
confidence: 99%
“…In this paper, we investigate the impact of dedicated placement on performance of architectures with direct connections between LUTs. Its original version appeared at the 30th International Conference on Field-Programmable Logic and Applications (FPL) [27] and introduced a dedicated detailed placement algorithm targeting FPGA architectures with such direct connections, combining iterative solving of Linear Programs (LPs) to select nodes that should be moved from their original positions determined by a general placer oblivious of the direct connections, and Integer Linear Programs (ILPs) to appropriately position them. The main technical novelty that this extended version of the paper brings is a greatly simpliied and improved main algorithm that orchestrates the construction and solving of diferent LPs and ILPs.…”
Section: Introductionmentioning
confidence: 99%