Timing Fault Models for Systems with Multiple Timers

Wang, Yu; Batth, S.S.; Wise, A.; Fecko, Mariusz A.

doi:10.1007/11430230_14

Cited by 7 publications

(2 citation statements)

References 12 publications

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“…In this paper, we first introduce an extended finite-state machine (EFSM) model with timer variables based on our earlier work [FUDA03,UWBWF05,UBWF06a] for the Controller process of the so-called rail-road crossing system [ALUR98]. This system has been studied as a benchmark in many real-time systems [HJL93,HL96,AKLN99,XEN04,CRV05a] .…”

Section: Introductionmentioning

confidence: 99%

Specification of Timed EFSM Fault Models in SDL

Batth

Vieira

Cavalli

et al. 2007

Lecture Notes in Computer Science

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Abstract. In this paper, we apply our timing fault modeling strategy to writing formal specifications for communication protocols. Using the formal language of Specification and Description Language (SDL), we specify the Controller process of rail-road crossing system, a popular benchmark for real-time systems. Our extended finite state machine (EFSM) model has the capability of representing a class of timing faults, which otherwise may not be detected in an IUT. Hit-or-Jump algorithm is applied to the SDL specification based on our EFSM model to generate a test sequence that can detect these timing faults. This application of fault modeling into SDL specification ensures the synchronization among the timing constraints of different processes, and enables generation of portable test sequences since they can be easily represented in other formal notations such as TTCN or MSC.

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Section: Introductionmentioning

confidence: 99%

Specification of Timed EFSM Fault Models in SDL

Batth

Vieira

Cavalli

et al. 2007

Lecture Notes in Computer Science

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“…It is shown here that our graph augmentations are capable to detect these single timing faults in an IUT. The issue of combination of these single timing faults, called multiple timing faults, has been addressed in [5] as an extension to this work.…”

Section: C1 Graph Augmentation To Detect Fault IVmentioning

confidence: 99%

Single Fault Models for Timed FSMs

Wang

Batth

Wise³

et al.

2005 IEEE Instrumentationand Measurement Technology Conference Proceedings

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Compositional Testing of Communication Systems

Gotzhein

Khendek

2006

Lecture Notes in Computer Science

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Abstract. Today, test methods for communication protocols assume, among other things, that the protocol design is specified as a single, monolithic finite state machine (FSM). From this specification, test suites that are capable of detecting output and/or transfer faults in the protocol implementation are derived. Limited applicability ofthese methods is mainly because oftheir specific assumptions, and due to the size ofthe derived test suite and the resulting test effort for realistic protocols. In this work, the compositional test method ( C-method), which exploits the a:vailable structure of a communication protocol, is proposed. The C-method first tests each protocol component separately for output and/or transfer faults, using one ofthe traditional test methods, then checks for composability, and finally tests the composite system for composition faults. To check for composability and to derive the test suite for the detection of composition faults, it is not required to construct the global state machine. Instead, all information is derived from the component state machines, which avoids a potential state explosion and lengthy test cases. Furthermore, the test suite checks for composition faults only. This substantially reduces the size ofthe test suite and thus the overall test effort.

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Timing Fault Models for Systems with Multiple Timers

Cited by 7 publications

References 12 publications

Specification of Timed EFSM Fault Models in SDL

Specification of Timed EFSM Fault Models in SDL

Single Fault Models for Timed FSMs

Compositional Testing of Communication Systems

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