Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Abstract

A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

“…However, the benchmarks they used were very simple to prove their effectiveness in some large designs, and the wire width parameter is also not studied. Baris et al proposed their work of clock mesh and synthesis with incremental register placement [19][20][21][22]. Feasible moving regions are built based on timing slack constraints, and this work combines incremental register placement with non-uniform clock mesh generation.…”

Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

“…A method is proposed in [18] to generate the clock mesh grid wires using an integer linear programming formulation to minimize the wirelength of the mesh. The works of [19] and [20] propose methods to simultaneously reduce the wires of a mesh grid and the stub wires of the mesh by placing the mesh grid wires close to the clock sinks. A method is proposed in [21]- [22] to determine the initial mesh size by considering the clock skew and wirelength.…”