Timing synchronization in super-regenerative receivers with a single quench cycle per symbol

Abstract

Super-regenerative receivers (SRR) are known for their ultra-low power (ULP) consumption. However, its wide frequency selectivity seriously degrades performance especially in the presence of interference. An attractive approach to address this problem is by lowering the quench rate of the SRR to the modulation rate. However, this brings in uncertainty due to lack of oversamples and leads to the timing synchronization problem in demodulation. This paper proposes a timing synchronization method for SRR with a single quench cycle per modulated symbol. A novel asynchronous preamble structure and an associated timing synchronization algorithm are proposed. Significant performance gains are obtained due to the improved frequency selectivity enabling the SRR system to adhere to the constraints set forth by the IEEE 802.15.4 standard while maintaining the ULP advantage.

Joint Symbol and Chip Synchronization for a Burst-Mode-Communication Superregenerative MSK Receiver

“…The synchronization problem in SR receivers for ASK modulations has received some attention, e.g., in [4] or [10]. Recently [11], an asynchronous preamble based on pseudo-noise sequences with amplitude-modulated pulses with a suitable pulse shaping function, combined with a fractional symbol period delay, is proposed. There, the SR oscillator (SRO) signal is fed to an envelope detector and chip and symbol synchronization is achieved thanks to a suitable processing scheme.…”

A fully digital open‐loop clock and data synchronizer for ultra‐low power super‐regenerative receivers

“…5 However, a ruin of bit-error-rate (BER) may occur in presence of any timing uncertainty between the input data and the quenching cycles. To resolve this problem, as shown in Figure 2B, synchronization techniques 6 are usually employed to properly set the phase and frequency of the quench signal according to the characteristics of the received data, commonly implemented by means of phase-locked loops (PLLs). 7 However, besides extra power and area budget, PLLs introduce loop stability issues and relatively low response time (i.e., lock time).…”