Timing Verification

Bhasker, J.; Chadha, Rakesh

doi:10.1007/978-0-387-93820-2_8

Cited by 7 publications

(12 citation statements)

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“…Based on either a breadth-first search or depth-first search, path enumeration algorithms have been proposed in [6,7]. Although these algorithms provide more information than the critical path algorithms, they suffer from the path explosion problem.…”

Section: K-most Critical Paths Algorithmmentioning

confidence: 99%

“…Taking process variations into account in timing analysis requires more computational effort. Multi-corner multi-mode static timing analysis (MCMM STA) is another variationaware approach to timing analysis that can serve as a compromise between traditional STA [7] and statistical static timing analysis (SSTA) [8]. In timing analysis, MCMM STA is very efficient in a sense that it propagates only minimum and maximum delay values.…”

Section: Introductionmentioning

confidence: 99%

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Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Oh¹,

Jin²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

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Section: K-most Critical Paths Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Oh¹,

Jin²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…Besides balancing skews, CTS also needs to balance the critical path delays of the enable signal to the CGCs along with the clock latency. To report timing paths across clocks accurately, we set the path multiplier in the Synopsys Design Constraint (SDC) [3] file for paths between all clocks. Table 3 summarizes the key metrics of the clock tree before (I = Initial, produced by a commercial tool) and after (O = Optimized) applying our top-level clock tree optimization.…”

Section: Testcase Description and Generationmentioning

confidence: 99%

OCV-aware top-level clock tree optimization

Chan

Han

Kahng

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures have become very complex and difficult to optimize with automatic clock tree synthesis (CTS) tools. In advanced process nodes, CTS becomes even more challenging due to on-chip variation (OCV) effects. In this paper, we present a new CTS methodology that optimizes clock logic cell placements and buffer insertions in the top level of a clock tree. We formulate the top-level clock tree optimization problem as a linear program that minimizes a weighted sum of timing slacks, clock uncertainty and wirelength. Experimental results in a commercial 28nm FDSOI technology show that our method can improve post-CTS worst negative slack across all modes/corners by up to 320ps compared to a leading commercial provider's CTS flow.

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“…We perform hierarchical synthesis at 45nm and flat synthesis at 28nm to demonstrate the scalability of GTX across different flows and foundry technologies. We generate verilog netlists, Synopsys Design Constraints (SDC) [1], and Standard Parasitic Exchange Format (SPEF) [40] files as inputs to timing tools. Real-world designs.…”

Section: A Design Of Experimentsmentioning

confidence: 99%

“…Our methodology is properly considered to be deep learning-based because the models in GTX are hierarchical, e.g., the output of the cell and wire delay models are input to the stage delay model [12]. Our modeling goals for each model are to (1) minimize the sum of squared errors, and (2) minimize the maximum range of errors. We achieve:…”

Section: Introductionmentioning

confidence: 99%

A deep learning methodology to proliferate golden signoff timing

Han

Kahng

Nath

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design methodologies, and implementation flows make timing closure very complex at advanced technology nodes. Design teams often wish to ensure that one tool's timing reports are neither optimistic nor pessimistic with respect to another tool's reports. The resulting "correlation" problem is highly complex because tools contain millions of lines of black-box and legacy code, licenses prevent any reverse-engineering of algorithms, and the nature of the problem is seemingly "unbounded" across possible designs, timing paths, and electrical parameters.In this work, we apply a "big-data" approach to the timer correlation problem. We develop a machine learning-based tool, Golden Timer eXtension (GTX), to correct divergence in flip-flop setup time, cell arc delay, wire delay, stage delay, and path slack at timing endpoints between timers. We propose a methodology to apply GTX to two arbitrary timers, and we evaluate scalability of GTX across multiple designs and foundry technologies / libraries, both with and without signal integrity analysis. Our experimental results show reduction in divergence between timing tools from 139.3ps to 21.1ps (i.e., 6.6×) in endpoint slack, and from 117ps to 23.8ps (4.9× reduction) in stage delay. We further demonstrate the incremental application of our methods so that models can be adapted to any outlier discrepancies when new designs are taped out in the same technology / library. Last, we demonstrate that GTX can also correlate timing reports between signoff and design implementation tools.

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Timing Verification

Cited by 7 publications

References 0 publications

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

OCV-aware top-level clock tree optimization

A deep learning methodology to proliferate golden signoff timing

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