TiN/titanium–aluminum oxynitride/Si as new gate structure for 3D MOS technology

Miyoshi, Juliana Harumi; Lima, Lucas Petersen Barbosa; Diniz, J. A.; Cavarsan, F. A.; Dói, I.; Filho, José G. Silva; Silva, A. R.

doi:10.1016/j.mee.2011.05.015

Cited by 3 publications

(5 citation statements)

References 7 publications

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“…Several JL device fabrication methods based on e-beam lithography (3), UV lithography (2), reactive ion etching (RIE) and inductively coupled plasma (ICP) (4) have been used. Focused Ion Beam (FIB) system has been widely used to inspect micro and nano devices and also to fabricate Si nanowires, sub-32 nm and 3D devices, such as FinFET (1)(2)(3)(4)(5)(6). In addition, FIB system can deposit metallic and dielectric layers, such as Pt and SiO 2 , respectively.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, FIB system can deposit metallic and dielectric layers, such as Pt and SiO 2 , respectively. Thus, FIB system can be used to get a fully nanofabrication or nanoprocessing of devices (5,6). In this context, this work presents the JL device fabrication using FIB system, to get Si nanowire channel, SiO 2 gate dielectric and gate, source and drain Pt electrodes on SOI substrate.…”

Section: Introductionmentioning

confidence: 99%

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Junctionless Fabrication on SOI Wafers Using Focused Ion Beam Milling and Al Diffusion

et al. 2012

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pMOS Junctionless (JL) devices were fabricated on Silicon On Insulator (SOI) substrates using gallium (Ga+) Focused Ion Beam (FIB) milling and Al diffusion, to get Si nanowire with p+ doping, respectively. Furthermore, SiO2 and Pt layers were used as gate dielectric and electrodes (gate, drain and source) of Junctionless transistors, respectively, and also were deposited using Ga+ FIB. Width, length and height dimensions of Si nanowire were about 100~300 nm, 4 μm and 200 nm, respectively. Energy Dispersive X-Ray Spectroscopy (EDS) measurements were carried out to confirm the surface composition of Si nanowire, dielectric and electrodes. In addition, from EDS results, Ga incorporation on Si nanowire surface occurred. This incorporation was from Ga+ FIB with no significant damage on Si nanowire. Drain-source current (Id) x drain source voltage (Vds) measurements of JL transistors were carried out, and indicate that the devices are working, like a gated resistor or JL device, with high Pt source and drain contact resistances, which lead to the distortions of Id x Vds curves. However, these distortions can be reduced using a longer time of contact sintering process and a Si nanowire height lower than 50 nm. Finally, our fabrication method using FIB process steps (Si milling, SiO2 and Pt depositions) and Al diffusion can be used to obtain Junctionless devices.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Junctionless Fabrication on SOI Wafers Using Focused Ion Beam Milling and Al Diffusion

et al. 2012

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“…11,12 Focused ion beam (FIB) for device fabrication has two main approaches: milling and lithography. While several works have been carried out using milling and ion-assisted material deposition for transistor fabrication, [7][8][9]13,14 here we explore a maskless and resistless lithography method for nanoscale multiple fin definition, which is used for FinFET prototype fabrication.…”

Section: Introductionmentioning

confidence: 99%

Ga+ focused ion beam lithography as a viable alternative for multiple fin field effect transistor prototyping

Leonhardt

Santos

Diniz

et al. 2016

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…[1][2][3] They provide better electrostatic control capabilities in the channel region compared to planar devices, as they are multiple 3D gate transistors. [2][3][4][5][6][7] In addition, the GaFIB/SEM dual beam system can deposit metallic and dielectric layers, such as Pt and SiO 2 , respectively, using Ga þ ion or electron beams. 3,5 Several methods based on e-beam lithography, 5 UV lithography, 3 reactive ion etching (RIE), and inductively coupled plasma 6 have been used to fabricate JNTs devices.…”

Section: Introductionmentioning

confidence: 99%

“…4 Also, these devices present good subthreshold slope, low leakage current, and high mobility/low diffusion of impurities at high temperatures. 7 In this context, this work describes JNT device fabrication using a Ga þ ion beam to define and for pþ local doping of the Si nanowire (pþ-SiNW), and an electron beam to deposit SiO 2 gate dielectric and source/drain Pt electrodes on the silicon on insulator (SOI) substrate. A Ga þ focused ion beam (GaFIB)/ scanning electron microscopy (SEM) dual system has been widely used to inspect micro-and nanodevices and also to fabricate sub-32 nm Si nanowires and 3D devices, such as FinFETs.…”

Section: Introductionmentioning

confidence: 99%