Tiny-: a novel formal method for specification. Analysis, and verification of dynamic partial reconfiguration processes

Abstract

On FPGA-platforms, the feature of dynamic partial reconfiguration offers a wide range of applications. We propose a new formal method for design, analysis, and verification of the reconfiguration process on such devices. The π-calculus, also known as the calculus of mobile processes, is a type of process algebra typically used to describe dynamic communicating processes. We propose the π-calculus as a foundation to model dynamic partial reconfiguration of hardware modules. A subset of this calculus that we call tiny-π can be executed in resourcerestricted, embedded environments which feature reconfiguration properties. As a proof-of-concept, we present a small virtual machine implementation for tiny-π. We have also implemented a compilation flow from a textual description of tiny-π specifications into executable bytecode. The virtual machine, running on an embedded Microblaze processor on an FPGA, can execute the bytecode and trigger corresponding reconfiguration commands for a dynamically reconfigurable FPGA platform.

Simulation-based functional verification of dynamically reconfigurable systems

“…Formal verification can also be used at system design time. The tiny pi-calculus approach applies a subset of pi-calculus to formally model the reconfiguration rules/directives (i.e., when to reconfigure what) of a DRS design [Seffrin et al 2010]. Symbolic simulation has been used to verify reconfigurable streaming applications meet their executable software specification [Todman et al 2012].…”

Hardware-accelerated execution of Pi-calculus reconfiguration schedules

“…Thus, n + 1 queue activity cycles would be required to transmit n arguments in the monadic calculus, while only one cycle is required in the polyadic rr-calculus. (11) x (a,b,c) == x(w).w(a).w(b).w(c) (13) 3) Complex System Example: In the example given by Equation 14, three additional features are introduced. Firstly, the name y of the receiving link y (w) is bound.…”

“…Communication is implemented by an interconnect network, which is also controlled by the schedule. Execution of the schedule can be performed by a softcore processor, as has been shown in [11], but direct execution in hardware would eliminate this requirement. In [10], it has been shown that an existing ticalculus verification tool can be used for proving properties of the reconfiguration schedule.…”