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Multiprocessor system-on-chip (MPSoC) architectures are a huge challenge in embedded system design. This situation arises from the fact that available MPSoCs and related designs flows are not tailored to the specific needs of embedded systems. This work demonstrates how to provide self-healing properties in embedded MPSoC design. This is achieved by combining the features of a generic approach to create virtualizable MPSoCs out of off-the-shelf embedded processors with a methodology to derive system configurations, such as task-processor bindings, which are optimal in terms of safety and execution time. The virtualization properties enable a reshaping of the MPSoC at runtime. Thus, system configurations may be exchanged rapidly in a dynamic fashion. As a main result of this work, embedded multiprocessor systems are introduced, which dynamically adapt to changing operating conditions, possible module defects, and internal state changes. We demonstrate the figures of merit of such reconfigurable MPSoC embedded systems by means of a complex automotive application scenario mapped to an FPGA featuring a virtualizable array of eight soft-core processors.

On FPGA-platforms, the feature of dynamic partial reconfiguration offers a wide range of applications. We propose a new formal method for design, analysis, and verification of the reconfiguration process on such devices. The π-calculus, also known as the calculus of mobile processes, is a type of process algebra typically used to describe dynamic communicating processes. We propose the π-calculus as a foundation to model dynamic partial reconfiguration of hardware modules. A subset of this calculus that we call tiny-π can be executed in resourcerestricted, embedded environments which feature reconfiguration properties. As a proof-of-concept, we present a small virtual machine implementation for tiny-π. We have also implemented a compilation flow from a textual description of tiny-π specifications into executable bytecode. The virtual machine, running on an embedded Microblaze processor on an FPGA, can execute the bytecode and trigger corresponding reconfiguration commands for a dynamically reconfigurable FPGA platform.