TITAC: design of a quasi-delay-insensitive microprocessor

Nanya, Takashi; Ueno, Yuichiro; Kagotani, Hiroto; Kuwako, M.; Takamura, Akihiro

doi:10.1109/54.282445

Cited by 73 publications

(27 citation statements)

References 10 publications

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“…The original Balsa Sequence component has been enhanced to include concurrent sequence behaviour implemented using the 'T-element' [13]. The concurrent sequencer allows some overlapping between the write and read halves of the control.…”

Section: Concurrent Sequencermentioning

confidence: 99%

Automatic Compilation of Data-Driven Circuits

Taylor

Edwards

Plana

2008

2008 14th IEEE International Symposium on Asynchronous Circuits and Systems

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This paper describes a method of synthesising asynchronous circuits based on the Handshake Circuit paradigm but employing a data-driven, rather than the control-driven, style. This approach attempts to combine the performance advantages of data-driven asynchronous design styles with the handshake circuit style of construction.The integration into the existing Balsa design flow of a compiler for descriptions written in a new datadriven language is described. The method is demonstrated using a significant design example -a 32 bit microprocessor. This example shows that the datadriven circuit style provides better performance than conventional control-driven Balsa circuits.

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Section: Concurrent Sequencermentioning

confidence: 99%

Automatic Compilation of Data-Driven Circuits

Taylor

Edwards

Plana

2008

2008 14th IEEE International Symposium on Asynchronous Circuits and Systems

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“…Tokyo University has fabricated several versions of a new architecture they call TITAC [49]. The most recent version is a full-featured 32-bit architecture that uses delay-scaling techniques to improve performance by taking real circuit delays into account, rather than conservatively assuming unbounded gate delays [64].…”

Section: Titac a Group At Tokyo Institute Of Technology Andmentioning

confidence: 99%

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

Brunvand

Nowick

Yun

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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“…We have proposed a model called dependency graph in [9,10] as a variant of control/data-flow graphs to describe the specification of asynchronous control circuits. It is also regarded as a subclass of Petri nets or free-choice nets.…”

Section: Two-phase Dependency Graphsmentioning

confidence: 99%

“…We have proposed a synthesis method of four-phase asynchronous controllers that controls four-phase resources based on mapping of dependency graphs, which represent the execution orders of micro-operations [9,10] 1 . Execution of a micro-operation implemented by a four-phase resource is decomposed into cyclic execution of a working phase, a stable phase, an idle (i.e.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs

Kagotani

Okamoto

Nanya

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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-We propose a method of synthesizing pipeline controllers as four-phase asynchronous circuits from specifications described as two-phase dependency graphs. Pipeline twophase dependency graphs are transformed into four-phase ones by applying a transformation rule to each simple loop in the graphs. Four-phase dependency graphs are easily mapped onto four-phase asynchronous control circuits. We also discuss some simplification of four-phase dependency graphs.

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TITAC: design of a quasi-delay-insensitive microprocessor

Cited by 73 publications

References 10 publications

Automatic Compilation of Data-Driven Circuits

Automatic Compilation of Data-Driven Circuits

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs

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