TLC/MLC NAND Flash Mix-and-Match Design with Exchangeable Storage Array

Hachiya, Shogo; Koh, Jung‐Hyuk; Miyaji, Kagami; Takeuchi, Ken

doi:10.7567/ssdm.2013.h-3-3

Cited by 15 publications

(11 citation statements)

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“…To significantly reduce cost, 3-bit/cell triple-level cell (TLC) NAND Flash memory has been adopted in current SSDs. As a result, SSD reliability is degraded by the lower read margins of TLC NAND Flash [8]. Considering the reliability degradation due to both scaling and multi-level NAND Flash, conventional BCH is not enough for current SSDs.…”

Section: Introductionmentioning

confidence: 97%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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a b s t r a c tTo improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012(Tanakamaru et al., , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2Ânm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4Â and 9.5Â at room-temperature (RT) and 85°C, respectively. Similarly, the acceptable BER is increased by 1.8Â and 2.3Â, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

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Section: Introductionmentioning

confidence: 97%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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“…3) has been proposed. 19) The MLC=TLC NAND flash hybrid SSD achieves lower cost and higher performance than MLC NAND flash only SSD. The MLC=TLC NAND flash hybrid SSD utilizes conventional 2D memory cell arrays of NAND flash memory which have a planar form as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…To improve the SSD performance, hybrid SSDs using the NAND flash memories or storage-class memories (SCMs) have been proposed. [13][14][15][16][17][18][19][20][21][22][23][24][25] The SCMs are non-volatile and able to be accessed by byte unit, thus read=write latencies of SCMs are much faster than those of NAND flash memories. Utilizing SCMs as a non-volatile cache or small-capacity storage to store frequent accessed data, performance of SSDs can be accelerated drastically.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

Sakaki¹,

Yamada²,

Matsui³

et al. 2018

Jpn. J. Appl. Phys.

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In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with twodimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

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“…However, beyond 20nm, reliability degrades significantly due to stronger neighbor cell coupling/disturb and other interactions [1]. Moreover, the introduction of Triple-Level Cell (TLC) flash [2] substantially reduces cost, but drastically decreases reliability. Therefore, to handle low-cost NAND with high BERs, Low Density Parity Check (LDPC) is considered the most appropriate for next generation ECC [3].…”

Section: Introductionmentioning

confidence: 99%

Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2014

2014 IEEE 6th International Memory Workshop (IMW)

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Highly reliable solid-state drives (SSDs) with triplelevel-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash's capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower V TH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention < 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSD's data-retention time increases by more than 12×, decode iterations decrease 57%, and acceptable TLC NAND BER increases by more than 2.8 ×.Index Terms-Error correcting code (ECC), low density parity check code (LDPC), triple level cell (TLC) NAND flash, memory controller, reliability, solid state drive (SSD)

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TLC/MLC NAND Flash Mix-and-Match Design with Exchangeable Storage Array

Cited by 15 publications

References 0 publications

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

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