Tolerance to transient faults in microprogrammed control units

Antola, A.; Negrini, R.; Sami, Mariagiovanna; Scarabottolo, Nello

doi:10.1109/24.61309

Cited by 7 publications

(3 citation statements)

References 11 publications

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“…The ITRS explicitly calls for a fresh look at nano-architecture with emphasis on defect tolerance [2]. Digital circuits have been extensively studied for improving fault tolerance due to variation and transient upsets and many techniques have been suggested to improve their fault tolerance [3], but nothing substantial has been done on analog side.…”

Section: Prior Workmentioning

confidence: 99%

Scalable mean voter for fault-tolerant mixed-signal circuits

Askari

Dwivedi

Saeed

et al. 2010

2010 IEEE Aerospace Conference

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Redundancy techniques, such as N-tuple modular redundancy has been widely used to improve the reliability of digital circuits. Unfortunately nothing substantial has been done for the analog and mixed signal systems. In this paper, we propose a redundancy based fault-tolerant methodology to design a highly reliable analog and digital circuits and systems. The key contribution of our work is an innovative mean voter. This mean voter is a low power, small area, very high bandwidth and linearly scalable voting circuit. Unlike other conventional voters which works with odd N in an NMR, the mean voter works for both odd and even N for analog units and hence reduces the area and power further. For the proof of concept, we designed two fault tolerant analog circuits i.e. a low pass anti-aliasing analog filter and a 4-bit flash ADC. We also presented fault-tolerance mechanism in 4-bit binary adder and an FPGA cell for demonstrating its advantage in digital applications. Experimental results are reported to verify the concepts and measure the system's reliability when single upset transient may occur.

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Section: Prior Workmentioning

confidence: 99%

Scalable mean voter for fault-tolerant mixed-signal circuits

Askari

Dwivedi

Saeed

et al. 2010

2010 IEEE Aerospace Conference

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“…Input Analog Digital Full Representative 0.02600 0.00150 0.02750 Complete 0.02465 0.00140 0.02610 where p is the number of input values for which the simulation was performed, q is the number of injection levels considered and r is the number of time instances at which faults were injected. E rel,i is calculated using (7) and w i is calculated using (5). The Maximum Relative Error (MRE) can be used as an additional metric which provides the worst case magnitude of the error.…”

Section: B Theoretical Basismentioning

confidence: 99%

“…Systems in space, biomedical and avionics applications consist of an analog front-end to collect data for control and observation purposes and a digital unit which processes the collected data. Digital circuits have been studied extensively for their sensitivity to transient faults [3], [4] and many techniques have been suggested to improve their fault tolerance [4], [5]. In contrast, very little has been done to address the issue of fault tolerance in analog circuits and ADCs which are integral parts of almost all mixed-signal circuits.…”

Section: Introductionmentioning

confidence: 99%

Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters

Singh¹,

Koren

2003

IEEE Trans. VLSI Syst.

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Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a digital unit to process it. Though considerable amount of research has been performed to increase the reliability of digital blocks, the same can not be claimed for mixed signal blocks. The reliability enhancement which we employ starts with fault sensitivity analysis followed by redesign. The data obtained from the sensitivity analysis is used to grade blocks based on their sensitivity to faults. The highly sensitive blocks can then be replaced by more reliable alternatives. The improvement gained by opting for more robust implementations might be limited due to the number of possible implementations. In these cases alternative reliability enhancement techniques such as adding redundancy may provide further improvements. The steps involved in the reliability enhancement of ADCs are illustrated in this paper by first proposing a sensitivity analysis methodology for α-particle induced transients and then suggesting redesign techniques to improve the reliability of the ADC. A novel concept of node weights specific to α-particle transients is introduced which improves the accuracy of the sensitivity analysis. The fault simulations show that, using techniques such as alternative robust implementations, adding redundancy, pattern detection and transistor sizing, considerable improvements in reliability can be attained.

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ROM-based synthesis of fault-tolerant controllers

Wendling¹,

Rochet²,

Leveugle³

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow

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Tolerance to transient faults in microprogrammed control units

Cited by 7 publications

References 11 publications

Scalable mean voter for fault-tolerant mixed-signal circuits

Scalable mean voter for fault-tolerant mixed-signal circuits

Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters

ROM-based synthesis of fault-tolerant controllers

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