Top-down technique for scaling to nano in silicon MEMS

Abstract

Nanoscale building blocks impart added functionalities to microelectromechanical systems (MEMS). The integration of silicon nanowires with MEMS-based sensors leading to miniaturization with improved sensitivity and higher noise immunity is one example highlighting the advantages of this multiscale approach. The accelerated pace of research in this area gives rise to an urgent need for batch-compatible solutions for scaling to nano. To address this challenge, a monolithic fabrication approach of silicon nanowires with 10-lm-thick silicon-on-insulator (SOI) MEMS is developed in this work. A two-step Si etching approach is adopted, where the first step creates a shallow surface protrusion and the second step releases it in the form of a nanowire. It is during this second deep etching step that MEMS-with at least a 2-order-of-magnitude scale difference-is formed as well. The technique provides a pathway for preserving the lithographic resolution and transforming it into a very high mechanical precision in the assembly of micro-and nanoscales with an extreme topography. Validation of the success of integration is carried out via in situ actuation of MEMS inside an electron microscope loading the nanowire up to its fracture. The technique yields nanowires on the top surface of MEMS, thereby providing ease of access for the purposes of carrying out surface processes such as doping and contact formation as well as in situ observation. As the first study demonstrating such monolithic integration in thick SOI, the work presents a pathway for scaling down to nano for future MEMS combining multiple scales.

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

“…The e-beam lithography step imposes a sidewall and line edge roughness that can be reduced through proximity effect correction technique [26]. In the present technology, the size reduction can be carried out by the definition of initial protrusions via lithography and shallow etch steps to decrease the width and the thickness of the Si NW, respectively [3,28,29]. A diffusion technique is utilized to dope the Si top surface to a mean resistivity of 5 × 10 −4 Ω • cm to prevent any electrical contact issues [3,26].…”

“…A high-resolution lithography defines the Si NW width, while the subsequent reactive ion etching (RIE) process sets the Si NW thickness. Fabrication details can be found elsewhere [26,28,29]. It should be emphasized that this technique yields Si NWs on the top surface of the SOI device layer, in which other microscale features are generated in the same batch by preserving an up to two-order-of-magnitude scale difference.…”

“…To address these challenges a monolithic technology for incorporating Si NWs in thick SOI wafers was introduced recently, where the Si NW remains an integral part of the SOI device layer, in which other components such as MEMS are co-fabricated [26][27][28][29]. This is achieved through a combination of high-resolution lithography and a two-step etching process.…”

Si-based MEMS Resonant Sensor: A Review from Microfabrication Perspective

“…Esfahani et al [187] presents a fabrication of piezoresistive based silicon nanowires resonator for obtaining resonance behavior of NEMS resonator with frequencies of 100 MHz showing a Lorentzian non-linear behaviour with Allain deviation of 3-8 ppm. The various steps involve in the fabrication of the Si NW on SOI wafer are summarized as (a) e-beam patterning of silicon nanowire, (b) bilayer patterning lift-off mask, (c) metallic coating by thermal-evaporation followed by lift-off (d) Si etching (e) low temperature oxide coating via LPCVD (f) oxide etching (g) MEMS patterning (f) deep etching of Silicon via bosch process (i) hydrofluoric acid releases the NW [177] as shown in the fig. 25.…”

“…Figure 25: The trapezoidal Si NW cross-section as seen via high-resolution TEM photograph. Close-up views from various zones of the Si NW are depicted in the insets[177]. (Reprinted with permission from[177].…”