Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

Phing, Ng Yen; Warip, Mohd Nazri Mohd; Ehkan, Phaklen; Zulkefli, F. W.; Ahmad, Rais

doi:10.12928/telkomnika.v15i1.6134

Cited by 4 publications

(3 citation statements)

References 11 publications

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“…Phing et al [31] has performed latency analysis of various topologies such as mesh, full mesh, torus, XX torus, ring and XX ring with X-Y routing algorithm. Their comparison result shows that XX ring topology outperforms the conventional topologies in terms of latency.…”

Section: Comparison Resultsmentioning

confidence: 99%

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Shahane

Pisharoty

2019

IET Circuits, Devices & Systems

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Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a singleside buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X-Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X-Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X-Y routing algorithm provides the best solution for area and latency optimisation.

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Section: Comparison Resultsmentioning

confidence: 99%

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Shahane

Pisharoty

2019

IET Circuits, Devices & Systems

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“…Topology plays an important role in NoC, choosing a topology will affect the overall performance, such as increasing the latency, power consumption and degradation in communication quality [2]. The routing area, delay, and power consumption is increasing as the IP core increasing.…”

Section: Introductionmentioning

confidence: 99%

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Phing

Warip

Ehkan

et al. 2019

IJEECS

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<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

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“…The choice of a network topology for NoC is significantly impacts its performance [3] [4]. The term of network topology can define as how the router is interconnect to each other [5]. The network topology can be designed as application specified or regular.…”

Section: Introductionmentioning

confidence: 99%

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

Phing¹,

Warip²,

Ehkan³

et al. 2018

IJEECS

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<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

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Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

Cited by 4 publications

References 11 publications

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

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