Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a singleside buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X-Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X-Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X-Y routing algorithm provides the best solution for area and latency optimisation.

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Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

Cited by 4 publications

References 10 publications

Comparative Performance Analysis of Routing Topology for NoC Architecture

Comparative Performance Analysis of Routing Topology for NoC Architecture

Midimew Connected Torus Network for Next Generation Massively Parallel Computer System

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

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