Torc

Steiner, Neil; Wood, Aaron; Shojaei, Hamid; Couch, Jacob; Athanas, Peter; French, Matthew

doi:10.1145/1950413.1950425

Cited by 68 publications

(4 citation statements)

References 5 publications

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“…We first considered to use the databases provided by the Torc framework [19]. However these databases do not make the difference between slices M and slices L, which can lead to non-functional relocated modules.…”

Section: B Layout Description and Supported Targetsmentioning

confidence: 99%

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Lalevée

Horrein

Arzel

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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Abstract-Dynamic and partial reconfiguration of Field Programmable Gate Arrays (FPGA) enable to reuse logic resources for several applications which are scheduled in a sequential order or which are loaded on demand. A fraction of the design on the FPGA is then substituted by another logic function while the rest of the system on the chip stays unaffected. If a design provides several partial reconfigurable areas, the configuration bitstream representing the logic function to be configured in this region has to be adapted to the physical requirements of this chip area. This can be achieved by deploying a repository with all possible configuration bitstreams for all possible regions. It is obvious that storage space can quickly become a limiting parameter in reconfigurable designs. For this purpose, bitstream relocation provides a less storage greedy approach. Only one representation as bitstream of an application needs to be stored. During the configuration process, a relocation algorithm manipulates the bitstream in order to suit it to the respective reconfigurable area. However, reconfigurable regions have to fulfill strong constraints for a relocation to be possible, which makes the selection and placement of reconfigurable regions a complex process. Unfortunately this is not automated by tools so far. In this paper, an approach to automate the development of such relocatable bitstreams is presented along with new algorithms related to relocation specific steps. This approach results in functional designs with minimal intervention from the designer.

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Section: B Layout Description and Supported Targetsmentioning

confidence: 99%

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Lalevée

Horrein

Arzel

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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“…RapidSmith has been widely used in both research and classroom settings for the creation of technology mappers, placers, routers, TMR reliability analysis tools, rapid prototyping tools [7], etc. Torc [5] is a similar framework, and allows users to manipulate designs at a variety of levels in the design flow including both EDIF and XDL. The GoAhead tool [6] provides extensive support for creating partially-reconfigured applications on FPGAs, containing floorplanning tools and support for the creation of static and partially-reconfigurable circuit modules.…”

Section: A Ise and Xdlmentioning

confidence: 99%

“…The creation of custom CAD tools which target commercial FPGA devices, however, has traditionally been much more difficult. Recently, a number of projects [4] [5] [3] [6] have created CAD tools such as RapidSmith and Torc that allow researchers to target commercial Xilinx parts. Importantly, all of these projects ultimately rely on the Xilinx Design Language (XDL) for this.…”

Section: Introductionmentioning

confidence: 99%

Tincr — A custom CAD tool framework for Vivado

White

Nelson

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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In recent years, frameworks such as RapidSmith and Torc have been developed for the creation of custom CAD tools able to target actual Xilinx FPGA devices. These have been based on the Xilinx Design Language (XDL), which provides textual representations of both mapped user designs as well as detailed physical FPGA device descriptions. Vivado, Xilinx's new design suite, discontinues XDL and instead provides direct access to its data structures through a Tcl interface and through EDIF and constraint files. This paper formally introduces Tincr, a library of high-level Tcl routines that support the creation of custom circuit manipulation tools. A case study on the use of Tincr for the creation of a simple placement tool is given. Additionally, this paper describes Tincr's facilities for importing and exporting XDL-and XDLRC-like information to and from Vivado to allow the continued use of existing external CAD tool frameworks such as RapidSmith and Torc with Vivado.

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“…Hence, there is no official support for developing open source bitstream generation tools similar to Project IceStorm [27], which reversed the Lattice iCE40 FPGAs. Such a tool improves the flexibility for designers and researchers, i.e., it could extend (security) frameworks like HAL [6], Torc [19], or RapidSmith [9].…”

Section: Introductionmentioning

confidence: 99%

Insights into the mind of a trojan designer

Ender

Swierczynski

Wallat³

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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The threat of inserting hardware Trojans during the design, production, or in-field poses a danger for integrated circuits in real-world applications. A particular critical case of hardware Trojans is the malicious manipulation of third-party FPGA configurations. In addition to attack vectors during the design process, FPGAs can be infiltrated in a non-invasive manner after shipment through alterations of the bitstream. First, we present an improved methodology for bitstream file format reversing. Second, we introduce a novel idea for Trojan insertion. CCS CONCEPTS • Security and privacy → Hardware reverse engineering; Malicious design modifications; Embedded systems security;

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Torc

Cited by 68 publications

References 5 publications

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Tincr — A custom CAD tool framework for Vivado

Insights into the mind of a trojan designer

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Torc

Cited by 68 publications

References 5 publications

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Tincr &#x2014; A custom CAD tool framework for Vivado

Insights into the mind of a trojan designer

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About

Tincr — A custom CAD tool framework for Vivado