2017
DOI: 10.1109/tns.2017.2706287
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Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

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Cited by 17 publications
(6 citation statements)
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“…As mentioned before, TID can affect SRAM sensitivity to SEUs or even directly cause errors on some devices [32]- [34].…”
Section: A Tid Testmentioning
confidence: 95%
“…As mentioned before, TID can affect SRAM sensitivity to SEUs or even directly cause errors on some devices [32]- [34].…”
Section: A Tid Testmentioning
confidence: 95%
“…In the case of static random-access memories (SRAMs), the radiation-induced defects and trapped charges, mainly in oxide and dielectric layers and at their interfaces with the semiconductor, alter the electrical conditions within the SRAM cells, affecting transistor threshold voltages and consequently SRAM stability. The degradation of this latter results in a reduction of the static noise margin (SNM) -the minimum noise voltage present at each of the cell storage nodes necessary to flip the state of the cell -and, consequently, in the reduction of the critical charge (Qcrit) -the minimum charge deposited by a ionizing particle at one of the nodes necessary to flip the state of the cell [16][17] -of the SRAM circuit, as shown in some previous studies [8][9][10][11][12][13][14][15]. These synergy effects between TID and single-event effects in devices and circuits are fundamental to apprehend electronic reliability in various environments, like space, accelerators, or future power fusion reactors.…”
Section: Introductionmentioning
confidence: 94%
“…Total ionizing dose (TID) is known to enhance the susceptibility of circuits to single-event effects (SEE) by modifying the electrical characteristics of individual transistors inside the exposed circuit [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. In the case of static random-access memories (SRAMs), the radiation-induced defects and trapped charges, mainly in oxide and dielectric layers and at their interfaces with the semiconductor, alter the electrical conditions within the SRAM cells, affecting transistor threshold voltages and consequently SRAM stability.…”
Section: Introductionmentioning
confidence: 99%
“…Electronics 2022, 11, x FOR PEER REVIEW nanoscale feature device are the buried oxide and shallow trench isolation oxid [27,31,[35][36][37]. For the test chip we designed, the SEU cross-section of the 6T S creases slightly after TID irradiation, due to two main reasons: (1) the gate ox thickness of our test chip is only 1.5 nm, so the gate oxide layer cannot trap eno charges; (2) the transistor used in the test chip adopts the structure of body und FET (BUSFET), which eliminates the formation of parasitic leakage channels bet source and drain electrodes caused by the radiation-induced charges trapped i oxide (BOX).…”
Section: Heavy Ion Irradiationmentioning
confidence: 99%
“…Meanwhile, the SEU cross-section had a certain dependence on parameters such as test data patterns, irradiation test temperature, etc. [27][28][29][30][31][32].…”
Section: Introductionmentioning
confidence: 99%