Toward scalable source level accuracy analysis for floating-point to fixed-point conversion

Abstract

In embedded systems, many numerical algorithms are implemented with fixed-point arithmetic to meet area cost and power constraints. Fixed-point encoding decisions can significantly affect cost and performance. To evaluate their impact on accuracy, designers resort to simulations. Their high running-time prevents thorough exploration of the design-space. To address this issue, analytical modeling techniques have been proposed, but their applicability is limited by scalability issues. In this paper, we extend these techniques to a larger class of programs. We use polyhedral methods to extract a more compact, graph-based representation of the program. We validate our approach with a several image and signal processing algorithms.

Fixed-Point Code Synthesis Based on Constraint Generation

“…In the context of polynomials, linear filters and signal processing algorithms, the members of the DEFIS project [13] presented many approaches for fixedpoint code synthesis. To mention a few, the idea described in [6] works by infer- ring high-level convolution operations from the original source code, and modeling them as part of the program representation. In addition, Najahi et al [12] presented an automated approach to synthesize codes in fixed-point arithmetic for some linear algebra basic blocks.…”

“…For instance, machine learning algorithms and models have been recently implemented using fixed-points with little accuracy loss [8,10]. The conversion of code designed for embedded systems from floating to a fixed-point equivalent version is a long-established problem addressed in the litterature [3][4][5][6]12]. Nevertheless, rarely we found tools (except for [4]) that deal with adjusting the floating-point formats in the original program before the conversion pass.…”

Aspect-Driven Mixed-Precision Tuning Targeting GPUs

“…In the embedded system domain, floating point values are usually converted to fixed point one [24] to limit the area cost and power consumption of the architecture. Hardware designers developed tools to support the automatic conversion of floating point values to fixed point ones [3,13,19,27]. More recent work in this field aims at exploiting fixed point arithmetics on FPGA accelerators to speedup floating point applications, such as [20].…”

Analysis of Finite Word-Length Effects in Fixed-Point Systems

“…The analysis to compute coefficients K i and L i j is done on an SFG representing the application and where the control flow has been removed. To avoid loop unrolling which can lead to huge graph, a method based on polyhedral analysis has been proposed in [44].…”