Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development &amp; Optimization Guidelines

Shrivastava, Mayank; Mehta, R. R.; Gupta, Shalabh; Agrawal, Natwar; Baghini, Maryam Shojaei; Sharma, Dinesh K.; Schulz, T.; Arnim, K. von; Molzer, W.; Gossner, Harald; Rao, V. Ramgopal

doi:10.1109/ted.2011.2123100

Cited by 42 publications

(7 citation statements)

References 11 publications

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“…The aim of an NoC as the heart of SoC is to provide an efficient, mostly stand-off free, power, and throughput aware communication amidst different cores of the system on chip [19]. Modern SoC designs are coming with FinFETs, which can improve communication speed [20].…”

Section: Multicore Systemsmentioning

confidence: 99%

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Sridhar

Krishnaiah²

2022

Journal of Sensors

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The increasing demand for network and high-performance devices requires large data throughputs with minimal loss or repetition. Network on chips (NoC) provides excellent connectivity among multiple on-chip communicating devices with minimal loss compared with old bus systems. The motivation is to improve the throughput of the NoC that integrated on multicores for communication among cores by reducing the communication latency. The design of the arbiter in the crossbars switch of an NoC’s router has a vital role in judging the system’s speed and performance. Low latency and high-speed switching are possible with high performance and good switching equipment at the network level. One of the significant components in NoC under SoC design is the arbiter, which governs the system’s performance. Proper arbitrations can avoid network or traffic congestions like livelock and buffer waiting. The proposed work in this paper is to design an efficient and high productive arbiter for multicore chips, especially SoCs and CMPs. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs.

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Section: Multicore Systemsmentioning

confidence: 99%

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Sridhar

Krishnaiah²

2022

Journal of Sensors

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“…Moreover, practical fabrication over a silicon of HfO 2 is also difficult, whereas in the proposed device first

normalSi O_{2}

fabricated on silicon hence it also allows practical fabrication. Further, the source and drain have the Gaussian doping profile which forms the ohmic junction and improves the ON current [13]. The channel region has the uniform doping profile at

1 \times 10^{15} normalc m^{- 3}

.…”

Section: Device Structure and Model Calibrationmentioning

confidence: 99%

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Yadav

Shah

Beohar

et al. 2019

Micro & Nano Letters

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High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

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“…To minimize the SCEs, multigate field effect transistors [3]- [13], such as double-gate transistors [3]- [6], Flexfets [7], and FinFETs or trigate transistors [8], were introduced. Among these structures, the FinFET technology has become a promising candidate to overcome the SCEs due to its superior performance in low-leakage and highdriving currents, compared with other technologies [9]- [11]. The FinFET structure, however, suffers more serious selfheating effects (SHEs) than planar MOSFET devices [12], [13], especially for the Silicon on insulator (SOI)-based FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

Jia

Helenbrook

Cheng

2014

IEEE Trans. Electron Devices

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An approach is proposed to project thermal behavior in a semiconductor integrated-circuit structure onto a functional space based on the proper orthogonal decomposition (POD). The approach substantially reduces the numerical degrees of freedom (DOF) needed for thermal simulations and requires no assumptions about physical geometry, dimensions, or heat flow paths. The POD approach is applied to a multi-fin FinFET structure having heat sources driven by power pulse excitations with time shifts, width variations, and amplitude modulations. The POD models were compared with detailed numerical simulations (DNS) and it was shown that the POD approach provides thermal solutions that were as accurate and detailed as the DNS. It offers a reduction in numerical DOFs by nearly six orders of magnitude to capture the peak temperatures in multi-fin FinFETs.Index Terms-Compact thermal model (CTM), FinFET, proper orthogonal decomposition (POD), reduced-order model (ROM), thermal simulation.

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Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

Cited by 42 publications

References 11 publications

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

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