2009
DOI: 10.1002/bltj.20373
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Towards 100G packet processing: Challenges and technologies

Abstract: Driven by media-rich and bandwidth-intensive

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Cited by 23 publications
(15 citation statements)
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References 27 publications
(27 reference statements)
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“…Bits continuative GF(2 w ) multiplier needs w clock periods to execute one multiplication operation. Its hardware complexity is ( ) w ο , and the delay of critical path is (1) ο , so bits continuative GF multiplier can run at a very high clock frequency. Bits continuative GF multiplier is sacrificing hardware simplified degrees for higher computational speed.…”
Section: ) Encryption Implementation Of Sms4mentioning
confidence: 99%
See 1 more Smart Citation
“…Bits continuative GF(2 w ) multiplier needs w clock periods to execute one multiplication operation. Its hardware complexity is ( ) w ο , and the delay of critical path is (1) ο , so bits continuative GF multiplier can run at a very high clock frequency. Bits continuative GF multiplier is sacrificing hardware simplified degrees for higher computational speed.…”
Section: ) Encryption Implementation Of Sms4mentioning
confidence: 99%
“…The standard speed of Ethernet is from 10/100/1000M to10G, and the speed of access network in future must be higher and higher [1]. Since it is user-oriented which means vulnerable to security attacks, how to effectively protect the security and guarantee the confidentiality of the messages simultaneously in access network becomes the hotspot of research fields in recent years [2].…”
Section: Introductionmentioning
confidence: 99%
“…When external memories are used, all tables are commonly stored in the same memory device and are accessed serially. The use of a unique external memory device to store all the hash tables is due to the pin limitations of network hardware devices which pin count can already exceed 1,000 pins [10]. Recently, the optimization of an implementation that combines both a fast on chip memory and a larger external memory has been studied in [11].…”
Section: Introductionmentioning
confidence: 99%
“…To implement Cuckoo hashing, the tables can be stored in a lower speed external memory [10] or can be realized using embedded memories in ASICs [9] or FPGAs [10] based networking devices. The design choice depends on the requirements in terms of speed and size of the hash table to be implemented.…”
Section: Introductionmentioning
confidence: 99%
“…Switching 100 GE requires that the selected switch architecture is scalable enough to accommodate high capacity transmission [1], as the 100 GE line speed quickly aggregates to the Terabit scale within the switch fabric. Single-stage switch fabrics, e.g.…”
Section: Introductionmentioning
confidence: 99%