Towards a balanced ternary FPGA

Abstract

We propose and analyze an organization for a Field-Programmable Gate Array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial siliconon-sapphire process that offers multiple simultaneous transistor thresholds. A simple example of a balanced ternary FIR filter is mapped to the FPGA and some preliminary estimates made of its performance and area.

A review on the design of ternary logic circuits*

“…In addition, for any integer represented by the balanced ternary, the opposite of the integer number can be obtained by replacing '−1' of each bit of the integer with '1' and '1' with '−1'. [16] In addition, the balanced ternary multiplication operation does not generate a carry. Under the condition that all the nine kinds of addition operation input, only two types have a carry generation, [10] as shown in Fig.…”

Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

“…[25,26] Moreover, this system can implement "carryfree" ternary adder and multiplexer, which is highly effective for arithmetic operations. [27] The logic "−1" (logic "1") of the ternary logic system is defined as the V G region where the n-channel mode (the p-channel mode) turns on and p-channel mode (the n-channel mode) turns off. A third intermediate logic level (logic "0") arises from the V G region, where both the n-and p-channel modes are turned on (V G1 = V G2 = 0 V).…”

Design and Application of Memristive Balanced Ternary Univariate Logic Circuit

“…Among them, balanced ternary logic has unique advantages, including the ability of having a unified representation for positive and negative numbers without the sign bit, and multiplication operation without generating a carry. Moreover, the symmetry of one-bit addition and multiplication operations can be used for symmetric arithmetic operation circuit design [12,13].…”