IEE Colloquium Reconfigurable Systems 1999
DOI: 10.1049/ic:19990347
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Towards a consistent design methodology for run-time reconfigurable systems

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Cited by 3 publications
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“…However, dynamic reconfiguration has emerged as an attractive technique for minimizing the reconfiguration time, which has a negative effect on FPGA performance [1], [11], [12]. An example of dynamic reconfiguration is the multicontext architecture, which may store a set of different configurations for the entire reconfigurable chip (contexts) in an internal memory.…”
Section: Introductionmentioning
confidence: 99%
“…However, dynamic reconfiguration has emerged as an attractive technique for minimizing the reconfiguration time, which has a negative effect on FPGA performance [1], [11], [12]. An example of dynamic reconfiguration is the multicontext architecture, which may store a set of different configurations for the entire reconfigurable chip (contexts) in an internal memory.…”
Section: Introductionmentioning
confidence: 99%
“…[2,1]) in order to remedy these problems. Accurate estimation of these metrics requires placement and detailed routing of the design modules for each of the investigated design architectures and configuration schedules, which is impractical for all but very simple designs.…”
Section: Introductionmentioning
confidence: 99%
“…In this paper we present a new DRL design framework, which implements a Library server-based DRL design methodology, introduced in [1] (design flow is reprinted in Fig. 1(b)).…”
Section: Introductionmentioning
confidence: 99%