Efficient metrics and high-level synthesis for dynamically reconfigurable logic

Abstract

The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis (HLS) tools since it allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous works however neglect the delay of interconnects (e.g. multiplexer) which can indeed contribute heavily on the overall performance of the design. In addition, in the case of dynamic reconfigurable logic (DRL) circuits, unless an appropriate design methodology is followed, large number of configurable logic blocks (CLBs) could be used for communication between contexts, rather than for implementing functional units (FUs). The aim of this paper is to present a new technique to perform interconnect-sensitive synthesis, targeting dynamic reconfigurable circuits. Further, the proposed technique exploits multiple hardware contexts to achieve efficient designs. Experimental results on several benchmarks, which have been done on our DRL LSI circuit (Meribout, 2000 and Motomura, 1997), demonstrate that by jointly optimizing the interconnect, communication, and function-unit cost, higher quality designs than other previous techniques (e.g. force-directed scheduling) can be achieved.

Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance

“…In particular, in HLS several simplified models for area and timing have been proposed in the literature. In [26], simple metrics are proposed to drive the optimization algorithms, even if some elements are not correctly considered (e.g., steering logic or effects of optimizations performed by the logic synthesis tools). In [3] the area is estimated with a linear regression approach that is also able to model the effects of the logic optimizations.…”

Gerenciamento de tags na arquitetura ChipCflow - uma máquina a fluxo de dados dinâmica

“…• Dinamicamente Reconfigurável: a reconfiguração dinâmica surgiu como uma técnica atrativa para minimizar o tempo de reconfiguração dos FP-GAs (MERIBOUT and MOTOMURA, 2004). Nos dispositivos dinamicamente reconfiguráveis, a configuração pode ser atualizada seletivamente enquanto o FPGA estiver ativo (energizado e em operação).…”

Minimizing FPGA Reconfiguration Data at Logic Level

“…For such systems, an important design concern is to minimize FPGA reconfiguration bitstreams, and this problem has been widely investigated from high level design. Studies in [1,2,3,4,5] present different algorithms to perform temporal partitions with the objective of reusing function units in different temporal partitions. Meanwhile, the reuse of FPGA routing patterns is investigated in [6].…”