Towards a standard for embedded core test: an example

Abstract

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a skndard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. Note that this paper provides! a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the standardization committee on its current status.

Test scheduling and scan-chain division under power constraint

“…A standard under development is the IEEE P1500 Standard for Embedded Core Test, consisting of a Core Test Language and a Core Test Wrapper [10] (Figure 5). The P1500 wrapper is similar to the TestShell.…”

The design and optimization of SOC test solutions

“…An example of a system under test is given in Figure 1 where each core is placed in a wrapper such as TestShell [15] or P1500 [16] …”

An Integrated Framework for the Design and Optimization of SOC Test Solutions

“…To ease test access the cores can be placed in wrappers such as Boundary scan [3], TestShell [20] or P1500 [15,21]. The Boundary scan technique, developed for PCB designs, suffers from long testing time due to the shifting process, and it becomes even worse for SOC designs since the amount of test data to be transported increases.…”

“…However, a delay may be introduced when the core is in transparent mode or its by-pass structure is used as in the TestShell [21]. On the other hand, Marinissen et al recently proposed a library of wrapper cells allowing a flexible design where it is possible to design non-clocked bypass structures of TAM width [22].…”