Towards an ESL framework for timing and power aware rapid prototyping of HW/SW systems

Grüttner, Kim; Hylla, Kai; Rosinger, Sven; Nebel, Wolfgang

doi:10.1049/ic.2010.0129

Cited by 9 publications

(6 citation statements)

References 6 publications

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“…A comprehensive approach from academia is the ESL framework for rapid prototyping presented in [9]. It supports non-functional system properties like power consumption estimated by pluggable external models for the different system components.…”

Section: Related Workmentioning

confidence: 99%

Creation of ESL power models for communication architectures using automatic calibration

Schürmans

Zhang

Auras

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models. This work proposes a methodology that allows extension of ESL models with a power model and to automatically calibrate it to match a power trace obtained by gate-level simulation or measurements. Two case studies show that the methodology is suitable even for complex communication architectures.

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Section: Related Workmentioning

confidence: 99%

Creation of ESL power models for communication architectures using automatic calibration

Schürmans

Zhang

Auras

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…SysML there are other UML profiles for embedded systems specification. One of these is Marte[lO] that has been adopted by several projects such as [11,12], which are also based on MDE.…”

Section: Background and Related Workmentioning

confidence: 99%

Model-based framework for embedded system product line

Hoyos

Casallas

Jiménez

2012

IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society

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The use of reconfigurable platforms for embedded system design leverages product line engineering (PLE), in which the development of products starts from a set of core assets (the platform) rather than the development of individual products from zero. Two major activities of PLE are domain engineering (i.e., platform development) and product engineering (i.e., prod uct customization) reusing the core assets. Virtual prototyping in PLE allows rapid validation of both the platform and individual products with greater benefits in development costs, time to market and quality. However, since virtual prototypes (VP) are implemented in low-level languages, if platform development and product engineering are done at this level, productivity is negatively affected. A commonly-accepted solution for closing this productivity gap is to raise the level of abstraction in the whole design process and to automate the implementation of VPs from the high-level descriptions. In this paper, we present the HiLeS2 Framework, which is based on Model Driven Software Product Lines (MD-SPL) concepts. HiLeS2 framework provides an environment for domain and product engineering, automated construction of VPs and creation of product line integrated development environments.

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“…One example of an high-level power estimation flow is described in [1]. In this flow power is annotated to functional and executable specifications of the design by different techniques.…”

Section: Related Workmentioning

confidence: 99%

“…In the following the flow will be described and summarized. For a more detailed view on the flow we refer to [1].…”

Section: A Simulative High-level Power Estimation Flowmentioning

confidence: 99%

“…This process takes several hours but has to be done only once for each package design and is independent on all dynamic parameters such as supply voltage, and threshold voltages. 1 Simulating one second of the systems lifetime will usually take more than one second on the simulating machine After the first run of the inner loop the temperature has evaluated to a heatmap. Changes of the temperature compared to the initial value of 300K are shown in Figure 8 (a).…”

Section: Application Of the Flowmentioning

confidence: 99%

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Behavioral-level thermal- and aging-estimation flow

Rosinger

Metzdorf

Helms

et al. 2011

2011 12th Latin American Test Workshop (LATW)

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In recent transistor technologies design metrics highly interdepend on each other and cannot be regarded isolated. For example temperature analysis requires detailed knowledge of the power consumption and leakage currents exponentially depend on the temperature. Additionally long-term aging-or degradation-effects such as electromigration and NBTI occur in recent designs and need to be considered too.For these reasons we propose a flow applying run-time efficient and accurate methods and tools from the power-, thermal-, and aging-estimation domain in combination with a model describing the physical properties of the IC package design. The flow iterates the parameter estimation to handle all interdependencies and results in a steady state after few runs and only seconds of execution time.

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Towards an ESL framework for timing and power aware rapid prototyping of HW/SW systems

Cited by 9 publications

References 6 publications

Creation of ESL power models for communication architectures using automatic calibration

Creation of ESL power models for communication architectures using automatic calibration

Model-based framework for embedded system product line

Behavioral-level thermal- and aging-estimation flow

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