Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

Abstract

With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multiported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bidirectional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bidirectional multi-ported memory designs. These results and analyses illustrate that our bi-directional multiported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost. INDEX TERMS Bi-directional ports, FPGAs, embedded memory, embedded systems, multi-ported memory, on-chip BRAMs.

Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform

“…Even the operating frequency of the proposed 2W4R modules works at 50.85% for 8K and 52.23% for 16K faster than the existing BDRT based 2W4R approach [16]. The bi-directional MPM is designed by [27] using a decision-making module (DMM) on Virtex-6 FPGA. The proposed design of the 2W4R module utilizes less BRAM of 33.33% for 8K and 33.3% for 16K than the existing approach [27].…”

“…The bi-directional MPM is designed by [27] using a decision-making module (DMM) on Virtex-6 FPGA. The proposed design of the 2W4R module utilizes less BRAM of 33.33% for 8K and 33.3% for 16K than the existing approach [27].…”

“…The works use remap table-based architecture for multiple writes -ports. Shahrouzi et al [27] discuss the MPMs with composing bi-directional features for advanced FPGAs. The work analyses the uni-directional MPM and bi-directional MPM using the decision-making module (DMM).…”

“…123than the proposed work, consuming more slices and LUTs than the proposed designs. The DMM-based 3W4R module[27] utilizes BRAMs of 96 and 192 for 8K and 16K memory depths. The proposed 3W4R module utilizes less BRAM of 50% for 8K and 50% for 16K than the existing approach[27].…”

Design and analysis of multiple read port techniques using bank division with XOR method for multi-ported-memory on FPGA platform

“…The coding methods are included for memory banks and multi-port memory emulation with best and worst cases to improve memory access. Shahrouzi et al [26] describe the bi-directional multi-ported memories with optimization for future generation FPGA systems. The work provides bi-directional features to multiple-write and read operations simultaneously.…”