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With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

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With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multiported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bidirectional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bidirectional multi-ported memory designs. These results and analyses illustrate that our bi-directional multiported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost. INDEX TERMS Bi-directional ports, FPGAs, embedded memory, embedded systems, multi-ported memory, on-chip BRAMs.