Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis

Shahrouzi, S. Navid; Perera, Darshika G.

doi:10.1016/j.micpro.2019.01.001

Cited by 20 publications

(13 citation statements)

References 11 publications

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“…This sheer design and routing complexity hinders FPGA manufacturers (e.g., Xilinx and Altera) from employing these multi-ported memories with their next-generation FPGAs. Furthermore, from our previous work on FPGA-based designs [2]- [6], it was observed that using the existing dual-port BRAMs on FPGAs can have a significant negative impact on the speedperformance of real-time compute/data-intensive applications (e.g., data mining, machine learning, control systems) on embedded platforms.…”

Section: Analysis Of Existing Work On Multi-ported Memories On Fmentioning

confidence: 99%

“…Since FPGAs are immediately available, the time-to-market is also reduced. Furthermore, the dynamic partial reconfiguration feature of the current FPGAs enables reconfiguring parts of the chip that require modification, while other parts are still operational; thus achieving significant space savings on chip for complex applications, as illustrated in [2]- [6]. The aforementioned features prolong the useful life of FPGA-based computing systems, while minimizing the long-term cost.…”

mentioning

confidence: 99%

“…Currently, FPGAs are widely used in many fields, including ASIC prototyping, medical electronics, aerospace, automotive, broadcast, consumer electronics, communications, and defense, to name a few. In recent years, there has been a dramatic increase in utilization of FPGAs, both in the industry and in the academia, to enhance the speedup of many real-time compute/data intensive applications, such as data mining/analytics [2]- [6], machine/deep learning [7], control systems, and image processing, specifically on embedded platforms.…”

mentioning

confidence: 99%

“…As a result, these existing dual-port memories on FPGAs, in their current form, are insufficient to provide the required support in accelerating real-time compute/data intensive applications on embedded platforms. Also, our previous work ( [2]- [6]) on FPGA-based accelerators for compute/data-intensive applications demonstrated that utilizing existing dual-port BRAMs can negatively impact the overall performance of the applications significantly.…”

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confidence: 99%

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Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

2020

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With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multiported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bidirectional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bidirectional multi-ported memory designs. These results and analyses illustrate that our bi-directional multiported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost. INDEX TERMS Bi-directional ports, FPGAs, embedded memory, embedded systems, multi-ported memory, on-chip BRAMs.

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Section: Analysis Of Existing Work On Multi-ported Memories On Fmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

2020

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“…Our previous work [15], [16], [17] and analyses [18] illustrated that Field Programmable Gate Array (FPGA) based systems are currently the best avenue to support compute/data-intensive applications/algorithms running on resource-constrained embedded devices. This is mainly because FPGAs comprise many attractive features that are beneficial to support applications/algorithms on embedded devices.…”

Section: Introductionmentioning

confidence: 99%

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

Alkamil

Perera

2020

IEEE Access

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New methods for computing fuzzy eigenvalues and fuzzy eigenvectors of fuzzy matrices using nonlinear programming approach

et al. 2023

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In this paper, we propose a new method to obtain eigenvalues and fuzzy triangular eigenvectors of a fuzzy triangular matrix (A ̃), which are the elements of the given fuzzy triangular matrix . To this purpose, we solve the 1 − cut of a fuzzy triangular matrix (A ̃) to obtain the 1 − cut of eigenvalues and eigenvectors.Then, based on the results obtained in a 1 − cut mode, we use three new models to determine the left and right widths for those eigenvalues and eigenvectors. So, after some manipulation, in each of the models, the fully fuzzy linear systems (FFLSs) transformed to 2n crisp linear equations and some crisp linear non-equations (that, the first model includes 2(n + 1), the second model includes 2(n + 3) and the third model includes 6n + 2 crisp linear non-equation). Then, we suggest a nonlinear programming problem (NLP) to calculation simultaneous equations and non-equations. Furthermore, we define three other new eigenvalues (namely, fuzzy escribed eigenvalue, fuzzy peripheral eigenvalue, and fuzzy approximate eigenvalue) for a fuzzy triangular matrix (A ̃) that does not have any suitable solution. the fuzzy escribed eigenvalue which is placed in a tolerable fuzzy triangular eigenvalue set (TTFES), the fuzzy peripheral eigenvalue placed in a controllable fuzzy triangular eigenvalue set (CTFES), and the fuzzy approximate eigenvalue placed in an approximate fuzzy triangular eigenvalue set (ATFES). Finally, numerical examples are presented to illustrate the proposed method.

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Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis

Cited by 20 publications

References 11 publications

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

New methods for computing fuzzy eigenvalues and fuzzy eigenvectors of fuzzy matrices using nonlinear programming approach

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