Towards data reliable crossbar-based memristive memories

Abstract

A series of breakthroughs in memristive devices have demonstrated the potential of using crossbar-based memristor arrays as ultra-high-density and low-power memory. However, their unique device characteristics could cause data disturbance for both read and write operations resulting in serious data reliability problems.This paper discusses such reliability issues in detail and proposes a comprehensive yet low area-/performance-/energyoverhead solution addressing these problems. The proposed solution applies asymmetric voltages for disturbance confinement, inserts redundancy for disturbance detection, and employs a refreshing mechanism to restore weakened data. The results of a case study show that the average overheads of area, performance and energy consumption for achieving data reliability, over a baseline unreliable memory system, are 3%, 4%, and 19% respectively.

Toward large-scale access-transistor-free memristive crossbars

“…The value of the reference current is chosen in between the expected current value for a memristor in the ON state (I ON ) and that in the OFF state (I OFF ), that is, I OFF < I ref < I ON . Some sensing circuits convert the bit-line current into a voltage and does the comparison in voltage [23].…”

“…A solution proposed in [23] addresses the problem caused by write disturbance. This solution confines the write disturbance effect to word-line-shared devices by applying asymmetric voltages to the word-line and the bit-line (e.g.…”

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

“…The transistor-level CMOS circuitry is implemented and then SPICE simulations are done using Cadence Virtuoso. For line resistances and capacitances, the same model and numbers used in [9] were assumed. The memristor models are having 250K Ron and 100M Roff, and are based on the fabricated memristors in [26].…”

“…To avoid its read disturbance challenge, reliable read operation techniques are proposed [9,8], including a process-temperature-aware dynamic bitline bias scheme on a 4-Mb memristor fabricated chip [8]. Li et al demonstrate a 1-Mb ternary content addressable memory (TCAM) test chip using 2-transistor/2-resistive-phase-change-storage (2T-2R) cells [10].…”

Analogue auto-associative memory using a multi-valued memristive memory cell

“…Furthermore, due to decreasing feature sizes, transistors have become less reliable, which not only affects the overall memory performance, but has also increased leakage currents while increasing overall power consumption. Therefore, the ability to identify a passive, low power, multi-valued memory storage device would certainly be welcomed by many [3].…”